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document3 - .reset(reset), 41 .en(en), 42 .load(load), 43...

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exp_5b_tb.v Tue Feb 22 14:09:46 2011 Page 1 1 `timescale 1ns / 1ps 2 3 //////////////////////////////////////////////////////////////////////////////// 4 // Company: 5 // Engineer: 6 // 7 // Create Date: 13:44:34 02/22/2011 8 // Design Name: exp_5b 9 // Module Name: F:/exp_5a/exp_5b_tb.v 10 // Project Name: exp_5a 11 // Target Device: 12 // Tool versions: 13 // Description: 14 // 15 // Verilog Test Fixture created by ISE for module: exp_5b 16 // 17 // Dependencies: 18 // 19 // Revision: 20 // Revision 0.01 - File Created 21 // Additional Comments: 22 // 23 //////////////////////////////////////////////////////////////////////////////// 24 module exp_5b_tb; 25 26 // Inputs 27 parameter n =4; 28 reg reset; 29 reg en; 30 reg load; 31 reg [n-1:0] D; 32 reg clock; 33 34 // Outputs 35 wire [n-1:0] Q; 36 37 // Instantiate the Unit Under Test (UUT) 38 always #5 clock =~clock; 39 exp_5b uut ( 40
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Unformatted text preview: .reset(reset), 41 .en(en), 42 .load(load), 43 .Q(Q), 44 .D(D), 45 .clock(clock) 46 ); 47 48 initial begin 49 // Initialize Inputs 50 reset = 1; 51 en = 0; 52 load = 0; 53 D = 0; 54 clock = 0; 55 56 // Wait 100 ns for global reset to finish 57 #100; 58 59 #10; 60 61 @( negedge clock); exp_5b_tb.v Tue Feb 22 14:09:46 2011 Page 2 62 reset =0; 63 64 #10; 65 @( negedge clock); 66 en =1; 67 68 #10; 69 @( posedge clock) 70 load =1; 71 D = 4'b0111; 72 73 #10; 74 @( negedge clock) 75 reset =1; 76 77 #10; 78 @( posedge clock) 79 reset =0; 80 en =1; 81 load = 0; 82 83 end 84 // Add stimulus here 85 always begin 86 // Repeated execution block. 87 #10; //wait for 10 * 1ns = 10ns 88 89 if (Q == 4'b1111) begin 90 #10 $display ( "Done with test on Expt 5b." ); 91 $finish ; 92 end 93 end 94 95 96 endmodule 97 98 99 100...
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This note was uploaded on 10/02/2011 for the course EE 2720 taught by Professor Desouza during the Fall '08 term at LSU.

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document3 - .reset(reset), 41 .en(en), 42 .load(load), 43...

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