EE2720syllabus

EE2720syllabus - 22.5% Test 2: 22.5% Homework: 15% Quizzes:...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
Fall 2009 EE 2720: Digital Logic I Instructor: Alexander Skavantzos 245 Electrical Engineering Building Phone: 578-5240, Email: alex@ece.lsu.edu Text: “Fundamentals of Digital Logic with Verilog Design,” Second edition, Stephen Brown and Zvonko Vranesic, McGraw-Hill, 2008. Catalog Description: Digital Logic I (2). Prereq: Admission to the College of Engineering. Boolean algebra; logic gates; minimization methods; analysis and syntheses of combinational logic networks; design examples. Grading: Test 1:
Background image of page 1
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: 22.5% Test 2: 22.5% Homework: 15% Quizzes: 10% Final Exam: 30% Test Policy: If a student misses any one of tests 1 or 2 for a medical reason then the student should provide the instructor with a doctors statement stating that the student was sick on the day of the test. In this case, a make-up test will NOT be given but instead the remaining test will count for 30%, the homework, for 20%, the quizzes 10%, and the final for 40%. Homework Policy : Late homework will not be accepted....
View Full Document

This note was uploaded on 10/02/2011 for the course EE 2720 taught by Professor Desouza during the Fall '08 term at LSU.

Ask a homework question - tutors are online