Set_3.pptx

Set_3.pptx - Digital Abstraction Voltage VDD Logic value 1...

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Digital Abstraction Logic value 1 Undefined Logic value 0 Voltage V DD V 1,min V 0,max V SS (Gnd)
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NMOS and PMOS Models
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NMOS Logic Gates V f V DD Pull-down network V x 1 V x n (PDN)
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NMOS NOT Gate
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NMOS NAND and NOR Gates
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NMOS AND Gate and OR Gate
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PMOS Logic Gates
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CMOS Logic Gates V f V DD Pull-down network Pull-up network V x 1 V x n (PUN) (PDN)
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CMOS NAND Gate (a) Circuit V f V DD (b) Truth table and transistor states on on on off 0 1 0 0 1 1 0 1 off off on off off on f off on 1 1 1 0 off off on on V x 1 V x 2 T 1 T 2 T 3 T 4 x 1 x 2 T 1 T 2 T 3 T 4
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CMOS NOR Gate (a) Circuit V f V DD (b) Truth table and transistor states on on on off 0 1 0 0 1 1 0 1 off off on off off on f off on 1 0 0 0 off off on on V x 1 V x 2 T 1 T 2 T 3 T 4 x 1 x 2 T 1 T 2 T 3 T 4
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CMOS AND Gate V f V DD V x 1 V x 2 V DD
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Transition Time l Time interval between two reference points on a waveform. These reference points are usually 10% and 90% of the voltage change. l Rise time ( tr ) – Time interval when waveform is changing from a logic low to a logic high level. l Fall time ( tr ) – Time interval when waveform is changing from a logic high to a logic low level.
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Propagation Delay l Time it takes for a change at the input of a device to produce a change at the output of the same. l t pLH is the propagation delay when the output changes from LOW to HIGH. l t pHL is the propagation delay when the output changes from HIGH to LOW. l t pLH and t pHL are not necessarily equal, and their values depends on the logic family.
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Propagation Delay and Transition Time
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Fanout l The number of gate inputs that a single output can drive or operate without exceeding its worst case loading specifications. l
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Set_3.pptx - Digital Abstraction Voltage VDD Logic value 1...

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