Expt-2(6)

Expt-2(6) - Click to edit Master subtitle style 10/2/11 EE...

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Unformatted text preview: Click to edit Master subtitle style 10/2/11 EE 2731 - Spring 2011 EE 2731 Spring 2011 Digital Logic Lab Experiment - 2 EE 2731 - Spring 2011 10/2/11 EE 2731 - Spring 2011 Before You Start o Read note on the experiment o Design things at home o any working design is OK o design with few chips is better EE 2731 - Spring 2011 10/2/11 EE 2731 - Spring 2011 Experiment 2 o Combinational Circuits n Part I: Realization with NAND gates n Part II: Decoder Realization n Part III: MUX relaization EE 2731 - Spring 2011 10/2/11 EE 2731 - Spring 2011 NAND Realization (Sec. 4.6.3) o Two-level realization of sum-of-products form has AND-level followed by OR o Bubbles inserted between AND outputs and OR inputs for NAND realization EE 2731 - Spring 2011 10/2/11 EE 2731 - Spring 2011 NAND Realization Example EE 2731 - Spring 2011 10/2/11 EE 2731 - Spring 2011 NAND Realization Example EE 2731 - Spring 2011 10/2/11 EE 2731 - Spring 2011 NAND Realization Example EE 2731 - Spring 2011 10/2/11 EE 2731 - Spring 2011 Multilevel NAND Realization EE 2731 - Spring 2011 10/2/11...
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This note was uploaded on 10/02/2011 for the course HNRS 1003 taught by Professor Zerba during the Spring '08 term at LSU.

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Expt-2(6) - Click to edit Master subtitle style 10/2/11 EE...

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