Expt-5 - Click to edit Master subtitle style EE 2731 Spring...

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Unformatted text preview: Click to edit Master subtitle style 10/2/11 EE 2731 - Spring 2011 EE 2731 Spring 2011 Digital Logic Lab Experiment - 5 EE 2731 - Spring 2011 10/2/11 EE 2731 - Spring 2011 Before You Start o Read note on the experiment o See the CPLD Board Manual o Design the experiment at home o Note any expected results for your experiment EE 2731 - Spring 2011 10/2/11 EE 2731 - Spring 2011 Experiment 5 o Verilog for Sequential logic (counter) n Basic counter n Counter with load n Counter parity n Parametrization of width o Resource use in CPLDs EE 2731 - Spring 2011 10/2/11 EE 2731 - Spring 2011 source: Brown and Ripple-carry adder: Generic module addern (carryin, X, Y, S, carryout); parameter n=32; input carryin; input [n-1:0] X, Y; output reg [n-1:0] S; output reg carryout; reg [n:0] C; integer k; always @(X, Y, carryin) begin C[0] = carryin; for (k = 0; k < n; k = k+1) begin S[k] = X[k] ^ Y[k] ^ C[k]; C[k+1] = (X[k] & Y[k]) | (X[k] & C[k]) | (Y[k] & C[k]); end carryout = C[n]; end endmodule Figure 5.28. A generic specification of a ripple- carry adder. 10/2/11 EE 2731 - Spring 2011 55 D latch and flip-flop module D_latch (D, Clk, Q); input D, Clk; output reg Q; always @(D, Clk) if (Clk) Q = D; endmodule Figure 7.35. Code for a gated D latch. module flipflop (D, Clock, Q); input D, Clock; output reg Q; always @( posedge Clock ) Q = D; endmodule Figure 7.36. Code for a D flip-flop. EE 2731 - Spring 2011 10/2/11 EE 2731 - Spring 2011 66 Blocking and Non-Blocking Assignment o Blocking assignment n Example: Q = D; n Verilog compiler in always block evaluates statements in the order in which they are written n If a variable is given a value by a blocking assignment statement, then new value used in evaluating all subsequent statements in the block....
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This note was uploaded on 10/02/2011 for the course HNRS 1003 taught by Professor Zerba during the Spring '08 term at LSU.

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Expt-5 - Click to edit Master subtitle style EE 2731 Spring...

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