Expt-7 - Click to edit Master subtitle style 10/2/11 EE...

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Unformatted text preview: Click to edit Master subtitle style 10/2/11 EE 2731 - Spring 2011 EE 2731 Spring 2011 Digital Logic Lab Experiment - 7 EE 2731 - Spring 2011 10/2/11 EE 2731 - Spring 2011 Before You Start o Read note on the experiment o Read the Digilab XCRP Reference Manual o Design the experiment at home o Note any expected results for your experiment EE 2731 - Spring 2011 10/2/11 EE 2731 - Spring 2011 Experiment 7 o 7-segment display input generator o Verilog function o Using the CPLD board clock o Using the 7-segment display on the CPLD board EE 2731 - Spring 2011 10/2/11 EE 2731 - Spring 2011 7-segment display input generator o Combinational logic EE 2731 - Spring 2011 4 bit number 10/2/11 EE 2731 - Spring 2011 7-segment display input generator o Make combinational logic EE 2731 - Spring 2011 10/2/11 EE 2731 - Spring 2011 Verilog Function Module adder (ADD, A, B, CIN); output [1:0] ADD; input A, B, CIN; wire S, COUT; begin assign S = A ^ B ^ CIN; assign COUT = (A&B) | (A&CIN) | (B&CIN); assign ADD = {COUT, S}; end endmodule EE 2731 - Spring 2011 10/2/11...
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This note was uploaded on 10/02/2011 for the course HNRS 1003 taught by Professor Zerba during the Spring '08 term at LSU.

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Expt-7 - Click to edit Master subtitle style 10/2/11 EE...

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