Intro(2)

Intro(2) - Click to edit Master subtitle style 10/2/11 EE...

Info iconThis preview shows pages 1–5. Sign up to view the full content.

View Full Document Right Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: Click to edit Master subtitle style 10/2/11 EE 2731 - Spring 2011 EE 2731 Spring 2011 Digital Logic Lab EE 2731 - Spring 2011 10/2/11 EE 2731 - Spring 2011 22 R. Vaidyanathan (Vaidy) o Associate Professor, ECE Dep. o http://www.ece.lsu.edu/vaidy/home.html o Office hours: MW 10:00 am-12:30 pm o Education: n IIT Kharagpur, India: B-Tech and M-Tech n Syracuse University: PhD o Research Interests: Algorithms and Architectures, Parallel and Distributed Computing, Reconfigurable Computing, Interconnects o Other interests: Music, puzzles (Sudoku, crossword), EE 2731 - Spring 2011 10/2/11 EE 2731 - Spring 2011 EE 2731 Spring 2010 o Course Page: Use the Moodle Page for handouts, experiments, and announcements o Text: Fundamentals of Digital Logic with Verilog Design , second edition, by Stephen Brown and Zvonko Vranesic, McGraw Hill, 2008. o Additional material posted on Moodle o Software: Xilinx ISE Design Suite o Prerequisite: EE 2730 (Digital Logic I) EE 2731 - Spring 2011 10/2/11 EE 2731 - Spring 2011 EE 2731 Spring 2010 o Course Page: Use the Moodle Page for handouts,...
View Full Document

Page1 / 14

Intro(2) - Click to edit Master subtitle style 10/2/11 EE...

This preview shows document pages 1 - 5. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online