Verilog-Background(2)

Verilog-Background(2) - EE 2730 Fall 2010 Verilog Review...

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Click to edit Master subtitle style 10/2/11 EE 2730 - Fall 2010 EE 2730 Fall 2010 Verilog Review for Combinational Circuits Chapter 2.9, 2.10, 4.12, 5.5, 6.6, Appendix A Parts adapted from a presentation by Dr. Jerry L. Trahan
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10/2/11 EE 2730 - Fall 2010 Hardware Design Using a CAD System EE 2730 - Fall 2010 Design conception Veri log Schematic capture DESIGN ENTRY Design correct? Functional simulation N o Y e s Synthes is Physical design Chip configuration Timing requirements met? Timing simulation Y e s
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10/2/11 EE 2730 - Fall 2010 Verilog Hardware Description Language o standardized o portable o helps rapid product development Describes relationship between inputs and outputs of a module o program code describes this relationship for a software module o HDL code describes this for a hardware module
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10/2/11 EE 2730 - Fall 2010 source: Brown and Structural specification f x 3 x 1 x 2 Figure 2.30. A simple logic function. module example1 (x1, x2, x3, f); input x1, x2, x3; output f; and (g, x1, x2); not (k, x2); and (h, k, x3); or (f, g, h); endmodule Figure 2.31. Verilog code for the circuit in Figure 2.30. ports gate level primitives
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10/2/11 EE 2730 - Fall 2010 source: Brown and Behavioral specification f x 3 x 1 x 2 Figure 2.30. A simple logic function. module example3 (x1, x2, x3, f); input x1, x2, x3; output f ; assign f = (x1 & x2) | (~x2 & x3); endmodule Figure 2.34. Using the continuous assignment to specify the circuit in Figure 2.30.
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10/2/11 EE 2730 - Fall 2010 source: Brown and Behavioral specification 2 module example3 (x1, x2, x3, f); input x1, x2, x3; output f ; assign f = (x1 & x2) | (~x2 & x3);
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This note was uploaded on 10/02/2011 for the course HNRS 1003 taught by Professor Zerba during the Spring '08 term at LSU.

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Verilog-Background(2) - EE 2730 Fall 2010 Verilog Review...

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