Verilog-Storage(2)

Verilog-Storage(2) - Click to edit Master subtitle style...

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Unformatted text preview: Click to edit Master subtitle style 10/2/11 EE 2730 - Fall 2010 EE 2730 Fall 2010 Verilog for Sequential Circuits Chapter 7.12.2-7.12.5, 7.13.3 Adapted from a presentation by Dr. Jerry L. Trahan EE 2730 - Fall 2010 10/2/11 EE 2730 - Fall 2010 22 Implied memory o if statement can specify storage element always @ (control or B) if (control) A = B; // A is variable of reg type o Does not say what happens when control = 0 o In absence of an assigned value, Verilog compiler assumes value of A caused by if statement must be maintained until next time if statement evaluated. o Implied memory realized by a latch in the circuit. EE 2730 - Fall 2010 10/2/11 EE 2730 - Fall 2010 33 D latch and flip-flop module D_latch (D, Clk, Q); input D, Clk; output reg Q; always @(D, Clk) if (Clk) Q = D; endmodule Figure 7.35. Code for a gated D latch. module flipflop (D, Clock, Q); input D, Clock; output reg Q; always @( posedge Clock ) Q = D; endmodule Figure 7.36. Code for a D flip-flop. EE 2730 - Fall 2010 10/2/11 EE 2730 - Fall 2010 44 Blocking and Non-Blocking Assignment o Blocking assignment n Example: Q = D; n Verilog compiler in always block evaluates statements in the order in which they are written n If a variable is given a value by a blocking assignment statement, then new value used in evaluating all subsequent statements in the block. n Preferred for combinational logic EE 2730 - Fall 2010 10/2/11 EE 2730 - Fall 2010 55 Blocking and Non-Blocking Assignment o Non-blocking assignment n Example: Q <= D; n Verilog compiler in always block evaluates statements using the values that the variables have when the always block is entered n...
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This note was uploaded on 10/02/2011 for the course HNRS 1003 taught by Professor Zerba during the Spring '08 term at LSU.

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Verilog-Storage(2) - Click to edit Master subtitle style...

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