sprufb0d - TMS320F2833x, 2823x System Control and Interrupts.pdf - TMS320x2833x 2823x System Control and Interrupts Reference Guide Literature Number

Sprufb0d - TMS320F2833x, 2823x System Control and Interrupts.pdf

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TMS320x2833x, 2823x System Control and Interrupts Reference Guide Literature Number: SPRUFB0D September 2007–Revised March 2010
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2 SPRUFB0D–September 2007–Revised March 2010 Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated
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Preface ....................................................................................................................................... 9 1 Flash and OTP Memory ...................................................................................................... 12 1.1 Flash Memory .......................................................................................................... 12 1.2 OTP Memory ........................................................................................................... 12 2 Flash and OTP Power Modes .............................................................................................. 12 2.1 Flash and OTP Performance ......................................................................................... 14 2.2 Flash Pipeline Mode ................................................................................................... 15 2.3 Reserved Locations Within Flash and OTP ........................................................................ 16 2.4 Procedure to Change the Flash Configuration Registers ......................................................... 16 3 Flash and OTP Registers .................................................................................................... 18 4 Code Security Module (CSM) .............................................................................................. 23 4.1 Functional Description ................................................................................................. 23 4.2 CSM Impact on Other On-Chip Resources ......................................................................... 26 4.3 Incorporating Code Security in User Applications ................................................................. 27 4.4 Do's and Don'ts to Protect Security Logic .......................................................................... 32 4.5 CSM Features - Summary ............................................................................................ 32 5 Clocking and System Control .............................................................................................. 32 5.1 Clocking ................................................................................................................. 32 5.2 OSC and PLL Block ................................................................................................... 40 5.3 Low-Power Modes Block .............................................................................................. 48 5.4 Watchdog Block ........................................................................................................ 49 5.5 32-Bit CPU Timers 0/1/2 .............................................................................................. 55 6 General-Purpose Input/Output (GPIO) .................................................................................. 60 6.1 GPIO Module Overview ............................................................................................... 60 6.2 Configuration Overview ............................................................................................... 66 6.3 Digital General Purpose I/O Control ................................................................................. 67 6.4 Input Qualification ...................................................................................................... 68 6.5 GPIO and Peripheral Multiplexing (MUX) ........................................................................... 73 6.6 Register Bit Definitions ................................................................................................ 78 7 Peripheral Frames ............................................................................................................ 103 7.1 Peripheral Frame Registers ......................................................................................... 103 7.2 EALLOW-Protected Registers ...................................................................................... 105 7.3 Device Emulation Registers ......................................................................................... 110 7.4 Write-Followed-by-Read Protection ................................................................................ 112 8 Peripheral Interrupt Expansion (PIE) .................................................................................. 113 8.1 Overview of the PIE Controller ..................................................................................... 113 8.2 Vector Table Mapping ............................................................................................... 116 8.3 Interrupt Sources ..................................................................................................... 118 8.4 PIE Configuration Registers ........................................................................................ 128 8.5 PIE Interrupt Registers .............................................................................................. 129 8.6 External Interrupt Control Registers ............................................................................... 137 Appendix A Revision History ..................................................................................................... 140 3 SPRUFB0D–September 2007–Revised March 2010 Table of Contents Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated
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List of Figures 1 Flash Power Mode State Diagram ...................................................................................... 14 2 Flash Pipeline .............................................................................................................. 16 3 Flash Configuration Access Flow Diagram ............................................................................ 17 4 Flash Options Register (FOPT) .......................................................................................... 19 5 Flash Power Register (FPWR) ........................................................................................... 19 6 Flash Status Register (FSTATUS) ...................................................................................... 20 7 Flash Standby Wait Register (FSTDBYWAIT) ........................................................................ 21 8 Flash Standby to Active Wait Counter Register (FACTIVEWAIT) ................................................. 21 9 Flash Wait-State Register (FBANKWAIT) ............................................................................. 22 10 OTP Wait-State Register (FOTPWAIT) ................................................................................ 23 11 CSM Status and Control Register (CSMSCR) ......................................................................... 28 12 Password Match Flow (PMF) ........................................................................................... 29 13 Clock and Reset Domains ............................................................................................... 33 14 Peripheral Clock Control 0 Register (PCLKCR0) ..................................................................... 34 15 Peripheral Clock Control 1 Register (PCLKCR1) ..................................................................... 36 16 Peripheral Clock Control 3 Register (PCLKCR3) ..................................................................... 38 17 High-Speed Peripheral Clock Prescaler (HISPCP) Register ........................................................ 39 18 Low-Speed Peripheral Clock Prescaler Register (LOSPCP) ........................................................ 39 19 OSC and PLL Block ....................................................................................................... 40 20 Oscillator Fail-Detection Logic Diagram ................................................................................ 41 21 XCLKOUT Generation .................................................................................................... 43 22 PLLCR Change Procedure Flow Chart ................................................................................. 45 23 PLLCR Register Layout .................................................................................................. 46 24 PLL Status Register (PLLSTS) .......................................................................................... 46 25 Low Power Mode Control 0 Register (LPMCR0) ...................................................................... 49 26 Watchdog Module ......................................................................................................... 50 27 System Control and Status Register (SCSR) ......................................................................... 53 28 Watchdog Counter Register (WDCNTR) ...............................................................................
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