Cell_arch - School of Electrical Engineering and Computer Science University of Central Florida Cell Broadband Engine Architecture CDA6938

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Unformatted text preview: School of Electrical Engineering and Computer Science University of Central Florida Cell Broadband Engine Architecture CDA6938 University of Central Florida 2 Cell History Cell History • IBM, Sony Computer Entertainment Incorporated SCEI/Sony, Toshiba Alliance ( STI ) formed in 2000. • The objectives for the new processor were the following: – Outstanding performance, especially on game/multimedia applications. – Real-time responsiveness to the user and the network. – Applicability to a wide range of platforms. – Support for introduction in 2005. • First technical disclosures, 2005. • Platforms: PS3, Cell Blade, Cell Accelerator Board • Trademarks – Cell Broadband Engine and Cell Broadband Engine Architecture are trademarks of Sony Computer Entertainment, Inc. CDA6938 University of Central Florida 3 Overview of the Cell Broadband Engine Overview of the Cell Broadband Engine • One PowerPC Processor Element ( PPE ) + Eight Synergistic Processor Element ( SPE ). • Increased efficiency and performance: – Attacks on the “Power Wall” • Non Homogenous Coherent Multiprocessor • High design frequency @ a low operating voltage with advanced power management – 45nm: 0.8v, 50w, 3.2GHz. – Attacks on the “Memory Wall” • Streaming DMA architecture – 128 simultaneous transfers between the eight SPE local stores and main storage. • 3-level Memory Model: Main Storage, Local Storage, Register Files – Attacks on the “Frequency Wall” • Highly optimized implementation • Large shared register files and software controlled branching to allow deeper pipelines CDA6938 University of Central Florida 4 Highlights Highlights • 90nm • 3.2 GHz • 241M transistors • 9 cores, 10 threads • >200 GFlops (SP) • > 20 GFlops (DP) • Up to 25 GB/s memory B/W • Up to 75 GB/s I/O B/W • >300 GB/s EIB CDA6938 University of Central Florida 5 PowerPC Processor Element PowerPC Processor Element • General purpose, 64-bit RISC processor (PowerPC) • 2-Way SMT • L1 : 32KB I ; 32KB D • L2 : 512KB • Coherent load / store • VMX-32 • 32 128-bit vector registers • The L2 cache and the address-translation caches use replacement-management tables that allow software to control use of the caches. CDA6938 University of Central Florida 6 Synergistic Processor Element Synergistic Processor Element • Synergistic Processor Unit (SPU) • Synergistic Memory Flow Control (MFC) – Data movement and synchronization – Interface to high performanceElement Interconnect Bus • Simple RISC User Mode Architecture – Dual issue VMX-like – Graphics SP-Float – IEEE DP-Float • Dedicated resources: unified 128x128-bit RF, 256KB Local Store • Dedicated DMA engine: Up to 16 outstanding requests CDA6938 University of Central Florida 7 Element Interconnect Bus Element Interconnect Bus • Four 16 byte data rings supporting multiple simultaneous transfers per ring • 96Bytes/cycle (64B data + 32B tags) peak bandwidth – 307.2GB at 3.2GHz– 307....
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This note was uploaded on 10/03/2011 for the course CDA 6938 taught by Professor Zou,c during the Spring '08 term at University of Central Florida.

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Cell_arch - School of Electrical Engineering and Computer Science University of Central Florida Cell Broadband Engine Architecture CDA6938

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