Seiler - Programming Larrabee: Beyond Data Parallelism Dr....

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Unformatted text preview: Programming Larrabee: Beyond Data Parallelism Dr. Larry Seiler Intel Corporation Intel Corporation, 2009 2 Programming Larrabee: Beyond Data Parallelism Agenda: What do parallel applications need? How does Larrabee enable parallelism? How does Larrabee support data parallelism? How does Larrabee support task parallelism? How can applications mix parallel methods? 3 Programming Larrabee: Beyond Data Parallelism Architecture Convergence CPU programmability & GPU parallelism Fixed Fixed Function Function Partially Partially Programmable Programmable Fully Fully Programmable? Programmable? Multi Multi-threading threading Multi Multi-core core T h r o u g h p u t P e r f o r m a n c e Larrabee Larrabee IA: Highly IA: Highly Programmable Programmable P r o g r a m m a b i l i t y GPU: High GPU: High Parallelism Parallelism Single Thread Single Thread 4 Programming Larrabee: Beyond Data Parallelism Programming Larrabee Larrabee supports braided parallelism: GPU-style data-parallelism, mixed with Multi-core task parallelism , mixed with Streaming pipe parallelism , mixed with Sequential code (still often necessary) Larrabee can submit work to itself Larrabee supports the IA architecture Larrabee lets applications mix the kinds of parallelism they need 5 Programming Larrabee: Beyond Data Parallelism Agenda What do parallel applications need? How does Larrabee enable parallelism? How does Larrabee support data parallelism? How does Larrabee support task parallelism? How can applications mix parallel methods? 6 Programming Larrabee: Beyond Data Parallelism Larrabee Block Diagram Cores communicate on a wide ring bus Fast access to memory and fixed function blocks Fast access for cache coherency L2 cache is partitioned among the cores Provides high aggregate bandwidth Allows data replication & sharing Memory Controller Multi- Threaded Wide SIMD Multi- Threaded Wide SIMD Multi- Threaded Wide SIMD Multi- Threaded Wide SIMD D$ D$ I$ I$ D$ D$ I$ I$ D$ D$ I$ I$ Fixed Function Texture Logic Memory Controller Memory Controller Display Interface System Interface D$ I$ Multi-Threaded Wide SIMD D$ I$ Multi-Threaded Wide SIMD D$ I$ Multi-Threaded Wide SIMD D$ I$ Multi-Threaded Wide SIMD L2 Cache . . . . . . 7 Programming Larrabee: Beyond Data Parallelism Processor Core Block Diagram Separate scalar and vector units with separate registers Vector unit: 16 32-bit ops/clock In-order instruction execution Short execution pipelines Fast access from L1 cache Direct connection to each cores subset of the L2 cache Prefetch instructions load L1 and L2 caches Instruction Decode Scalar Unit Vector Unit Scalar Registers Vector Registers L1 Icache & Dcache 256KB L2 Cache Local Subset Ring 7 Programming Larrabee: Beyond Data Parallelism Processor Core Block Diagram Separate scalar and vector units with separate registers Vector unit: 16 32-bit ops/clock...
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This note was uploaded on 10/03/2011 for the course CDA 6938 taught by Professor Zou,c during the Spring '08 term at University of Central Florida.

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Seiler - Programming Larrabee: Beyond Data Parallelism Dr....

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