CS M51A / EE M16
Winter 2011
Homework #5
Problem 1:
Implement the following program repeatedly using a single 8bit
adder/subtracter (AS) module, 8bit registers, as few as possible as small as possible
counters and combinational modules of your choice.
The AS module executes addition, when control signal c1 is 0 and subtraction when
control signal c1 is 1. Every five cycles the 7bit input variables b, c, and e are updated
with new values. All values (given and calculated) are positive. Values a, f, g, h, and d
should be available one each clock cycle, in their respective order.
statement 1. a = b + c;
statement 2. f = b + e;
statement 3. g = a − c;
statement 4. h = b + e;
statement 5. d = b − c;
Problem 2:
Using modulo 16 counters and multiplexers implement a system that
produces the following sequence:
Problem 3:
Design a system which outputs 1 if 4 of the last 5 characters are 1011 with at
most 2 mismatched bits. The definition of mismatched bit is a bit in the sequence which
doesn’t correspond the its specified value. For example, for pattern 1111, the following
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 Spring '11
 staff
 Addition, minimal number, shift registers, control signal c1

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