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ID #2 Problem 3 (16 points) Design a system that accepts as input: a 1bit input stream outputs 1 (forever) if it
takes an even number of clock cycles to recognize all of the following patterns at
least once: 011, 00 and 101. Otherwise, it outputs 0. Use at most 1 Tﬂip ﬂop, IKﬂip
ﬂops, AND, OR and NOT gates (all inputs, their complements, 0 and 1 are available). Examples: For input sequence 00101011, the output is 1, because all three patterns
appear at least once, and the last recognized pattern (011) ends at the 8th clock
cycle, which is an even number. Whereas stream 011000101 is not accepted since
the last recognized pattern is ends at the 9th cycle. Therefore, all patterns must be
seen at least once and the last pattern to be seen must ﬁnish on an even cycle. )5 C “LVN/f2
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ID #: Problem 5 (16 points) Use 8 input multiplexers to design a 5bit parity generator. A parity generator
produces output zero if the input has zero or an even number of ones, otherwise
produces one. Your design must use the minimum number of required multiplexers
(only inputs, 1 and 0 are available). Parity generator is a function p(x4, x3, x2, x1, x0) where x4, x3, x2, x1, x0 are the bits
for which we would like to compute the parity. Examples: p(1,1,0,0,0) = 0; p(0, 0, 0, 0, 0) = 0; p(1, 1, 1, O, 0) = 1; p(1, O, 0, O, 0) = 1
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 Spring '11
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