tut_sopc_introduction_verilog

tut_sopc_introduction_verilog - Introduction to the Altera...

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Introduction to the Altera SOPC Builder Using Verilog Design This tutorial presents an introduction to Altera’s SOPC Builder software, which is used to implement a system that uses the Nios II processor on an Altera FPGA device. The system development flow is illustrated by giving step-by-step instructions for using the SOPC Builder in conjuction with the Quartus R c II software to implement a simple system. The last step in the development process involves configuring the designed circuit in an actual FPGA device, and running an application program. To show how this is done, it is assumed that the user has access to the Altera DE2 Development and Education board connected to a computer that has Quartus II and Nios R c II software installed. The screen captures in the tutorial were obtained using the Quartus II version 7.1; if other versions of the software are used, some of the images may be slightly different. Contents: Nios II System Altera’s SOPC Builder Integration of the Nios II System into a Quartus II Project Running the Application Program 1
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Altera’s Nios II is a soft processor, defined in a hardware description language, which can be implemented in Altera’s FPGA devices by using the Quartus R c II CAD system. To implement a useful system it is necessary to add other funcional units such as memories, input/output interfaces, timers, and communications interfaces. To facilitate the implementation of such systems, it is useful to have computer-aided-design (CAD) software for implementing a system-on-a-programmable-chip (SOPC). Altera’s SOPC Builder is the software needed for this task. This tutorial provides a basic introduction to Altera’s SOPC Builder, which will allow the reader to quickly implement a simple Nios II system on the Altera DE2 board. For a fuller treatment of the SOPC Builder, the reader can consult the Nios II Hardware Development Tutorial . A complete description of the SOPC Builder can be found in the Quartus II Handbook Volume 4: SOPC Builder . These documents are available on the Altera web site. 1 Nios II System A Nios II system can be implemented on the DE2 board as shown in Figure 1. On-chip memory interface SDRAM interface Flash memory Parallel I/O interface Serial I/O interface SRAM interface SRAM chip SDRAM chip chip Flash memory Avalon switch fabric Nios II processor JTAG UART interface USB-Blaster interface Host computer lines Parallel I/O port lines Serial I/O port Cyclone II FPGA chip JTAG Debug module Figure 1. A Nios II system implemented on the DE2 board. 2
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The Nios II processor and the interfaces needed to connect to other chips on the DE2 board are implemented in the Cyclone II FPGA chip. These components are interconnected by means of the interconnection network called the Avalon Switch Fabric. The memory blocks in the Cyclone II device can be used to provide an on-chip memory for the Nios II processor. The SRAM, SDRAM and Flash memory chips on the DE2 board are accessed
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This note was uploaded on 10/11/2011 for the course ECE 332 taught by Professor Staff during the Fall '08 term at Boise State.

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tut_sopc_introduction_verilog - Introduction to the Altera...

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