test2-spring2009 - b. Latch is ____________________...

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1 of 2 Boise State University Department of Electrical and Computer Engineering ECE 230 Digital Systems Test 2, Date: April 6, 2009, Location: ET 110, Time: 1:40pm to 2:30pm Name: ______________________________ Instructions : Show all steps and logic circuits for full or partial credits. It is very important that you write clearly, so that your test can be graded appropriately and fairly. This is a closed book and closed notes test. ABSOLUTELY NO calculator. 1. (15 points) Complete the following using 8-bit signed number (using 2’s complement) representation. You need to indicate whether arithmetic overflow occurs. What is the range of 8-bit signed number using 2’s complement number representation? (a) 98 10 – (–33 10 ) _________________ (b) 00111110 – 01000111 _________________ (c) 11000111 –11010010 _________________ 2. (10 points) Short answers and fill in the blanks. a. What is the key difference between a half-adder and full-adder?
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Unformatted text preview: b. Latch is ____________________ sensitive. c. Flip-flop is ______________________ sensitive. d. A multiplexer circuit has a number of ___________ inputs, one or more select inputs, and ________ output. e. Why is 2s complement better for implementing arithmetic logics than 1s complement? 2 of 2 3. (10 points) Show how the function can be realized using Act 1 logic blocks (Act 1 logic block is shown). Note that there are no NOT gates in the chip; hence complements of signals have to be generated using the multiplexers in the logic block. 4. (15 points) Complete the following timing diagram. 5. (15 points) Design a comparator logic circuit that compares two 4-bit binary numbers ( A and B ). This comparator logic only has 1-bit output (called AltB , A less than B). When A < B, AltB = 1 . Otherwise, AltB = 0 . i 4 i 5 i 8 f i 2 i 6 i 1 i 7 i 3...
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test2-spring2009 - b. Latch is ____________________...

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