Ch7_Mem_PLD

Ch7_Mem_PLD - Chapter 7 Memory and Programmable Logic...

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Chapter 7 Memory and Programmable Logic Devices
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Memory Random Access Memory (RAM) Contrary to Serial Access Memory (e.g. Tape) Static Random Access Memory (SRAM) Data stored so long as Vdd is applied 6-transistors per cell Faster Differential Dynamic Random Access Memory (DRAM) Require periodic refresh Smaller (can be implemented with 1 or 3 transistor) Slower Single-Ended Can be read and written Typically, addressable at byte granularity Read-Only Memory (ROM)
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Block Diagram of Memory Example: 2MB memory, byte-addressable N = 8 (because of byte-addressability) K = 21 (1 word = 8-bit) 2 k  words N-bit per word Memory Unit N-bit Data Input (for Write) N-bit Data Output (for Read) K-bit address  lines Read/Write Chip Enable N N K
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Static Random Access Memory (SRAM) Typically each bit is implemented with 6 transistors (6T SRAM Cell) During read, the bitline and its inverse are precharged to Vdd (1) before set WL=1 During write, put the value on Bitline and its inverse on Bitline_bar before set WL=1 BitLine BitLine Wordline (WL)
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Dynamic Random Access Memory (DRAM) 1-transistor DRAM cell During a write, put value on bitline and then set WL=1 During a read, precharge bitline to Vdd (1) before assert WL to 1 Storage decays, thus requires periodic refreshing (read-sense-write) Bitline Wordline (WL)
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Capacity of a memory is described as # addresses x Word size Examples: Memory # of addr # of data lines # of addr lines # of total bytes
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Ch7_Mem_PLD - Chapter 7 Memory and Programmable Logic...

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