4GPLL - 2GHz, 4GHz Phase-Locked Loop Design Albert Woo Ju...

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Unformatted text preview: 2GHz, 4GHz Phase-Locked Loop Design Albert Woo Ju Jang, Moon Kyung Kim, John Haeseon Lee P.I. Prof. Apsel ECE 453 Analog CMOS Electrical & Computer Engineering Cornell University Fall 2005 Contents P LL • Objectives • PLL Overview - Phase-Frequency Detector - Charge Pump / Loop Filter - Voltage Controlled Oscillator • Schematic - Important Design Techniques - Achieving Phase Locked Signal • Simulation results • 4 GHz PLL Design Phased-Lock Loop Fall 2005 ECE453 Analog CMOS 2 GHz Charge Pump PLL Design P LL Objective • Design a charge pump phase-locked loop (PLL) operating at 2- GHz using IBM 0.25um BiCMOS 6hp technology. • This PLL will be designed for possible application in receiver circuit for WCDMA system. Design Goal Results Signal Frequency (GHz) 2 GHz 1.9 GHz~2 GHz Lock In Time 50 ns 194 ns Power consumption Low Power 11.54mW VCO Phase Noise -40 dBc @10 KHz -35 dBc @10 KHz VCO Tuning Range 500 MHz 400 MHz Note: PLL can be implemented for either digital or analog, but we will design analog PLL for application with RF and microwave signals. Phased-Lock Loop Fall 2005 ECE453 Analog CMOS P LL PLL Overview What is PLL? PLL is a closed-loop feedback control system that maintains a generated signal in a fixed phase relationship to a reference signal. Output signal frequency = Reference Signal Frequency Feedback control circuit. Feedback controls VCO to precisely track the phase of a stable reference oscillator. PLLs are very popular component in analog & RF systems. FM Demodulators Carrier Signal Recovery / Clock Recovery Frequency Synthesizers for Modulation and Demodulation Phased-Lock Loop Fall 2005 ECE453 Analog CMOS P LL How it works Low Frequency Output Signal Input Signal PFD Charge Pump Loop Filter VCO Charge Pump Loop Filter VCO High Frequency PFD Divider 1/N Phased-Lock Loop Fall 2005 ECE453 Analog CMOS Phase-Frequency Detector P LL Consists of two D-Flip Flops, one NAND gate and Inverter Detects difference in frequency or phase and produces two Detects signals proportional to the difference signals D Reference Q QA Reference CLRQ’ VCO D QA Q’ VCO CLRQ QB QB Design issue Phased-Lock Loop Fall 2005 ECE453 Analog CMOS Charge pump and Loop filter P LL By sourcing and pulling the current out of the capacitor, varies By the voltage on the capacitor, the Amount of the current and capacitor value critical. Loop Filter gets rid of high frequency components. UP UP DN DN Design issue : W/L of transistors should be chosen carefully to balance the current during charging and discharging Current Mirror Phased-Lock Loop Fall 2005 ECE453 Analog CMOS P LL Voltage Controlled Oscillator (VCO) VCO is treated as a linear, time-invariant system. VCO gain defined as KVCO [rad/s/v or Hz/v]. Designed -gm cross coupled PFET VCO. Frequency VCO center frequency ΔVcont Design issue Phased-Lock Loop Fall 2005 ECE453 Analog CMOS Frequency Divider Used in PLLs that needs to generate signal of higher Used frequency than PFD and CP can handle. frequency Divide by 2, Divide by 3 circuits are commonly used. State of the art circuits can divide up to 40 GHz signal. VCO signal Phased-Lock Loop Frequency Divider Fall 2005 P LL Output ECE453 Analog CMOS P LL Reference Vcont Output Phased-Lock Loop Fall 2005 ECE453 Analog CMOS Final schematic (Top View) Phased-Lock Loop Fall 2005 P LL ECE453 Analog CMOS Final Schematic Phased-Lock Loop Fall 2005 P LL ECE453 Analog CMOS 2 GHz PLL Simulation Results Phased-Lock Loop Fall 2005 P LL ECE453 Analog CMOS 2 GHz PLL Simulation Results Phased-Lock Loop Fall 2005 P LL ECE453 Analog CMOS 4 GHz PLL Simulation Results Maximum operation frequency of PFD/CP is 2 GHz. Used Divide by 2 circuit. Phased-Lock Loop Fall 2005 P LL ECE453 Analog CMOS 4 GHz PLL Simulation Results Phased-Lock Loop Fall 2005 P LL ECE453 Analog CMOS P LL Summary 2 GHz PLL has been designed with specs of Locking Range : 1.9 GHz ~ 2 GHz Locking Time : 500 ns VCO Tuning Range : 400 MHz VCO Phase Noise : -40 dBc @ 10 KHz 4 GHz PLL has been simulated using ½ divider. Phased-Lock Loop Fall 2005 ECE453 Analog CMOS Reference P LL Design of Analog CMOS Integrated Circuits, Behzad Razavi RF Microelectronics, Behzad Razavi The Design of CMOS Radio-Frequency Integrated Circuits, Thomas H. Lee Zhongtao Fu, Cornell University Phased-Lock Loop Fall 2005 ECE453 Analog CMOS ...
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This note was uploaded on 12/18/2010 for the course ECE 453 taught by Professor Staff during the Fall '08 term at Cornell University (Engineering School).

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4GPLL - 2GHz, 4GHz Phase-Locked Loop Design Albert Woo Ju...

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