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Essential_VHDL_2P - 68 Essential VHDL 7 Digital Engineering...

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Essential VHDL 7 This text is about starting to learn how to design large digital systems. A large part of that activity is knowing how to use and apply electronic design automation tools including hardware description languages (HDLs) for design specification, simulation, and synthesis. This chapter describes the essential VHDL needed for this text. VHDL is used in this text for designing, simulating, and implementing digital systems at the gate and register transfer level (RTL) of specification, and hence we concentrate on the synthesis subset of the language. VHDL, because it is a concurrent programming language with support for describing circuit delays and structure, can also be used to create abstract high-level models of digital systems. These simulation models, and those aspects of the language, can be extremely complex and are beyond the scope of this text. VHDL is chosen because it is an IEEE standard and can be used to write abstract system-level models to gate level specifications for programming a simple field programmable device (FPD). Verilog would also be a good choice, but most low cost tools support VHDL and not Verilog. As to other specialized or vendor specific languages that just target FPDs, they are not really any simpler to learn, and are not sufficient for complex tasks. VHDL will be a language you can use throughout your engineering career whether you are programming a 16V8 PLD or modeling a flight control system. The following style guidelines should be sufficient to study the problems posed in this text. These are a minimal synthesis set and will work with almost all VHDL synthesis tools (with minor modifications). See your tools for additional supported constructs. This chapter provides general background. Additional lan- guage details and examples are provided in subsequent chapters. 68 Digital Engineering with VHDL IEEE Library Declarations Every VHDL file should begin with library declarations. Generally these will be the IEEE libraries that are becoming a standard for VHDL synthesis. It may also be necessary to include vendor specific libraries to access various vendor spe- cific features. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; Figure 7.1 Librar y Declarations The library declaration makes the library IEEE visible and the use declarations cause the packages std_logic_1164, std_logic_arith, and std_logic_unsigned to be used when referenced. Packages contain useful predefined language elements such as standard types and over-loaded arithmetic operators such as arithmetic addition (‘‘+’’) and subtraction (‘‘-’’) that can be used with logic valued types such as std_logic_vector. Types VHDL defines data representation types, and the scalar and array types include objects such as integer, real, and bit. For various reasons none of these are quite right for describing digital circuit values. Most synthesis tools, and simulation models, use the type std_logic from the IEEE library. The type std_logic is a
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