Chapter10

Chapter10 - Chapter 10: True Assembly Language EEC 70 Fall...

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Unformatted text preview: Chapter 10: True Assembly Language EEC 70 Fall 2010 Professor Wilken 1 Final Abstractions Some MAL instructions represent multiple (usually two) TAL instructions, or variations of TAL instructions or TAL instructions corresponds one to one with a machine instruction with Can think of assembly as a two step process: process: 1. Map each MAL instruction into 1. corresponding TAL instruction(s) corresponding 2. Map each TAL instruction into its 2. corresponding 32-bit binary code. corresponding 2 Mapping MAL to TAL Arithmetic and Logical Instructions MAL ALU instructions with just register operands must conform to the MIPS R-type operands type instruction format: instruction operation $dest, $source1, $source2 add $10, $11, $12 is a valid TAL instruction $10, is move $10, $11 add $10, $0, $11 $10, add MAL ALU instructions with a constant operand must conform to the MIPS I-type format: must operation, $dest, $source1, <16 bit const., 2’s complement> complement> add $10, $11, 8 $10, addi $10, $11, 8 addi • add, addi are distinct operations, have different add, operation codes. ADD uses all registers, ADDI uses a constant constant 3 Mapping MAL to TAL Arithmetic and Logical Instructions (cont.) Constants larger than 16 bits in MAL ALU instruction will map to multiple TAL instructions: instructions: add $10, $11, 0x12345678 $10, lui $1, 0x1234 $1 ori $1, $1, 0x5678 add $10, $11, $1 Multiply produces a 64 bit result, thus MAL Multiply mul $10, $11, $12 is not sufficiently general • MIPS uses to special result registers HII and LO that MIPS H and LO that receive the 64 bit result receive separate mult command with just operand specifiers mult special move commands to move HI and LO to general registers registers mul $10, $12, $13 $10, mult $12, $13 mult mflo $10 4 Mapping MAL to TAL Arithmetic and Logical Instructions (cont.) Division also uses HI and LO, and special move commands move • LO receives quotient, HI receives remainder div $10, $11, $12 $10, div $11, $12 div mflo $10 rem $10, $11, $12 $10, div $11, $12 div mfhi $10 5 Mapping MAL to TAL Branch Instructions Not all MAL branch instructions are supported in TAL TAL • Only bltz, bgez, blez, bgtz, beq, and bne are included. Only bltz bgez blez bgtz beq and bne are Rest must be synthesized by a two instruction sequence sequence • MIPS includes Set Less Than iinstruction that allows nstruction MIPS Set other MAL branches to be synthesized other slt $x, $y, $z slt $x, ble $10, $11 $10, compares $y with $z and sets $x to 1 if $y < $z, otherwise sets $x to 0 slt $1, $11, $10 slt bnez $1, target # $1 is 1 if $10 > $11 what about bge $10, $11 in two instructions? what bge $10, 6 Mapping MAL to TAL Load/Store Instructions MAL instruction: MAL la $10, label la $10, does not fit into 32 bits. Must be synthesized does using two TAL instructions: using lui $10, <upper 16 address bits> ori $10, <lower 16 address bits> MAL instruction: MAL lw $10, label also must be synthesized. Can be: la $1, label lw $10, 0($1) which becomes: lui $1, <upper 16 address bits> ori $1, <lower 16 address bits> ori lw $10, 0($1) $10, 7 Mapping MAL to TAL Load/Store Instructions Better is: lui $1, <upper 16 address bits> lw $10, <lower 16 address bits>($1) sw $10,label has similar synthesis, sw has except cannot destroy contents of $10: except lui $1, <upper 16 address bits> sw $10, <lower 16 address bits>($1) • Notice the use of $1, which is reserved for the Notice assembler as a scratch register assembler 8 Mapping MAL to TAL I/O Instructions MIPS uses syscall instruction to allow syscall instruction user program to request OS services. • Essentially a subroutine call to the OS. Essentially Requested service code is passed in $v0 ($2) Requested Arguments in $a0-$a1 for integer/char operation. Arguments $a1 Results for integer/char are returned in $v0 Results Service print_int print_string read_int read_string exit (done) print_character Read_character System Call Code 1 4 5 8 10 11 12 Arguments Result $a0 = integer $a0 = string addr integer in $v0 $a0 = buffer addr. $a1 = length $a0 = character char in $v0 9 Assembly Process 1. Map MAL to TAL (as described) 2. Map TAL instructions to binary code 2.a Resolve label addresses 2.b Map each TAL instruction field into Map corresponding binary field corresponding 10 Resolving Label Addresses Data and instructions each start at fixed addresses addresses Assembler scans the data and instructions, counting as to goes. instructions, When a label is reached, an entry is made in the symbol table symbol Data example: Data address 0x00001000 0x00001004 0x00001008 contents 0x00000003 0x0a?????? 0x0a?????? 0x???????? .data a1: a2: a3: # assume starts at 0x1000 .word 3 .byte ‘\n’ .byte .space 7 symbol table a1 = 0x00001000 a2 = 0x00001004 a2 a3 = 0x00001005 11 Resolving Label Addresses Resolving (cont.) (cont.) Code example Code .text __start: loop: lw $7, 4($6) addi $6, $6, 4 beq $6,$8, finish beq finish beq $7,$0 loop beq loop finish: addi $2, $0, 10 finish: addi syscall syscall #assume code starts at 0x8000 # address 0x8000 # address 0x8004 # address 0x8008 # address 0x800c address # address 0x8010 address # address 0x8014 address symbol table: loop 0x00008000 finish 0x00008010 12 Producing Machine Code Each TAL instruction field maps into a binary code (see appendix C), within instruction format format Consider a simple example: Consider addi $8, $20, 15 opcode rt rs immediate Corresponding instruction format (I-type): Corresponding opcode rs rt from table opcode is: from rs is 5-bit binary for 20: bit rt is 5-bit binary for 8: bit immediate is 16-bit binary for 15: immediate 001000 001000 10100 10100 01000 01000 0000000000001111 machine code is: 0010 0010 1000 1000 0000 0000 0000 1111 1000 0000 13 Producing Machine Code Labels For instructions that involve labels, must look up the label in the symbol table to produce the binary binary Consider a simple example: beq Consider opcode $7, $0, loop rs rt target addr. Corresponding instruction format (I-type): Corresponding opcode rs rt address offset Assembler must compute difference between target’s address from symbol table and target address (branch’s address+4), divided by 4 (branch 14 Producing Machine Code Labels (cont.) loop: lw $7, 4($6) addi $6, $6, 4 beq $6,$8, finish beq beq $7,$0 loop beq loop <next> # address 0x8000 # address 0x8004 # address 0x8008 address # address 0x800c # address 0x8010 Branch byte offset is -16ten = 0x8000 0x8000 0x8010 • Word offset is –16/4 = -4 Word 16/4 from table opcode is: from rs is 5-bit binary for 7: bit rt is 5-bit binary for 0: bit immediate is 16-bit binary for -4: bit 000100 000100 00111 00111 00000 00000 1111111111111100 machine code is: 0001 0000 1110 0000 1111 1111 1111 1100 1111 1111 15 Assembly of Code/Data Assembler scans program from start to end Assembler Code/data sections are concatenated together Code/data • code and data are kept in separate areas of memory code1 code1 data1 code2 code2 data1 data2 data2 16 Separate Assembly/Compilation It is often desirable or necessary to separately assemble or compile procedures that are part of a larger program larger • How can the addresses be determined, e.g., the target How of a JAL? of Main Main A JAL A B JAL B • Address references outside the procedure being Address compiled as called external references external e.g., procedure entry point, global data address e.g., • The address of an external reference cannot be The resolved when the module is assembled/compiled 17 Separate Assembly/Compilation (cont.) Assembled/compiled procedure must keep info about unresolved external references, including partial symbol table information: partial Main 11001 A 00001 B 10101 01011 001?? 11100 2:: A 110?? 00110 11101 A: 0 10010 10110 00101 B: 0 1:: B Label : relative address Instruction # :: unresolved external label These partially assembled/compiled files are sometime called “object files” 18 Linking The linking operation: The Main 11001 • collects (links) the separately collects assembled/compiled procedures together into a single program together • Produces a symbol table for the Produces unresolved references unresolved • Resolves the references that are not Resolves dependent on program’s location in dependent location memory (which in not yet known) memory e.g., memory accesses relative to global data pointer can be resolved pointer Local variables addresses are already resolved, why? why? • The resulting file is often referred to as The an “executable file” A 01011 001?? 11100 00001 110?? 00110 11101 B 10101 10010 10110 00101 2:: A A: 4 5:: B B: 8 19 Loading It is not known where in memory the OS is going to load the program until the user executes it the Main 11001 When starting address is assigned, the loader resolves all of the absolute address references: address • Jump, Jump and Link, and Load Address A 01011 00110 11100 00001 11001 00110 11101 B 10101 10010 10110 00101 4002:: A A: 4004 4005:: B B: 4008 20 Memory Layout Code and data are put into separate regions of memory regions • Loader initializes instructions, global data Global data are not reinitializes if program is rerun, only if reloaded reserved max for OS stack heap global global data data Code reserved for OS 0 21 Instruction Formats R-Type Details Immediate Type: includes addi, lw, branches Immediate op 6 rs 5 immediate rt/rd 5 16 Jump Type op address 6 26 Register Type: alu instructions op rs 6 5 rt 5 rd 5 shamt funct 5 6 R-type instructions do not need all 32-bits: add Rd, Rss, Rt = 6 + 5 + 5 + 5 = 21 bits add Rss Rt MIPS uses lower 6 bits as a secondary opcode, secondary funct field funct field 22 R-Type Details (cont.) All R-type instructions share the same All type opcode (000000), are distinguished by secondary opcode secondary Allows processor hardware to be simplified (see EEC170) simplified 23 Shift Operations TAL includes two types of shift operations. Both are R-type instructions operations. • shift by a constant amount, uses shamt field shift shamt field to specify the amount of the shifting (0-31): to 31): srl $10, $11, 4 srl R-type 0 rt rd 6 5 5 5 shamt srl 5 6 • shift by a variable amount, where the shift shift amount is in a register: srlv $10, $11, $12 srlv R-type rs rt rd 0 srlv 6 5 5 5 5 6 24 ...
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This note was uploaded on 10/07/2011 for the course EEC 70 taught by Professor Wilken during the Fall '05 term at UC Davis.

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