cs313-2005-t1-midterm2-solution

cs313-2005-t1-midterm2-solution - CPSC 313, 05w Term 1—...

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Unformatted text preview: CPSC 313, 05w Term 1— Midterm 2 — Solutions Date: November 9, 2005; Instructor: Mike Feeley 1. (10 marks) Short answers. 1a. Briefly explain how an n-channel MOSFET transistor closes the circuit between its source and drain when its gate voltage is high. The high gate voltage produces a field in the positive-doped silicon substrate that draws electrons toward the gate. The electrons pile up along the glass insulator that separates the gate from the substrate and they form an electron-rich channel between the negative-doped source and drain wells. There is now an electron rich path between source and drain and thus current can flow between them. 1b. Can an general-purpose processor (just the processor itself) be design using only combinational logic? Why or why not? No, because combination logic along is finite state and thus is unable to express all forms of computation, some of which are require infinite state (i.e., memories and unbounded time). Combination logic can implement any Boolean function or any finite automata, but you need a sequential circuit to implement a Turing machine or a general-purpose program. 1c. Give one advantage the y86 (and/or a RISC processor) gets from confining memory access to special instructions that do nothing else but load from and store to memory (i.e., mrmovl and rmmovl . ALU instructions have predictable performance, because they do not access mem- ory; memory access has variable performance depending on whether target is in cache or not. OR Can use ALU to compute memory address for mrmovl and rm- movl, because they don’t need the ALU to compute anything else, unlike the ALU instructions (e.g., addl etc.). 1d. Explain the difference between a pipeline stall and a pipeline bubble? A pipeline stall is when a pipeline stage’s input memory remains the same from one cycle to the next. A pipeline bubble is when a pipeline stage’s input memory changes to that of a nop instruction, i.e., an instruction that does nothing. On any cycle when an instruction stalls in one stage, a bubble is injected into the subsequent stage....
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This note was uploaded on 10/09/2011 for the course CPSC 344 taught by Professor Karen during the Fall '10 term at UBC.

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cs313-2005-t1-midterm2-solution - CPSC 313, 05w Term 1—...

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