cs313-2006-t1-midterm2

cs313-2006-t1-midterm2 - CPSC 313 06w Term 1 Midterm 2 Date...

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CPSC 313, 06w Term 1— Midterm 2 Date: November 17, 2006; Instructor: Norm Hutchinson This is a closed book exam; no notes; you may use a calculator if you wish. Answer in the space provided; use the backs of pages if needed. There are 6 questions on 8 pages, totaling 50 marks. You have 50 minutes to complete the exam. On the last two pages you will find summaries of the Y86 instructions and stage outputs of the sequential processor implementation. You may find it profitable to (carefully) remove these pages from the exam. You should write this exam in pen - I will not consider requests to regrade solutions that are written in pencil. NAME: STUDENT NUMBER: SCORE: / 50 1. (10 marks) Short answers. 1a. (2 marks) In the standard pipeline (F, D, E, M, W), does stalling stage D one cycle cause stalls or bubbles for any other cycles? List all of them, indicate which stalls and which bubbles. 1b. (2 marks) Briefly explain why the pipelined version of the y86 processor has control hazards. 1c. (2 marks) How is instruction-level parallelism related to data dependencies? 1d. (2 marks) Explain by giving reference to the pipelined implementation of the Y86 processor a very significant difference between RISC and CISC instruction set architectures.
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1e. (2 marks) What is data forwarding? Why is it useful? 2. (5 marks) HCL 2a. (3 marks) Give the HCL description of a single circuit that takes two 32-bit integer inputs, A and B, and computes a result OUT that evaluates to: 0 if either A or B is negative A if A is equal to B A - B if A is greater than B B - A if B is greater than A 2b.
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