cs313-2006-t1-midterm2-solution

cs313-2006-t1-midterm2-solution - CPSC 313, 06w Term 1...

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CPSC 313, 06w Term 1— Midterm 2 — Solutions Date: November 17, 2006; Instructor: Norm Hutchinson 1. (10 marks) Short answers. 1a. (2 marks) In the standard pipeline (F, D, E, M, W), does stalling stage D one cycle cause stalls or bubbles for any other cycles? List all of them, indicate which stalls and which bubbles. Bubble in E and stall in F. 1b. (2 marks) Briefly explain why the pipelined version of the y86 processor has control hazards. Fetching the next instruction in F, but not knowing the address until E or M. 1c. (2 marks) How is instruction-level parallelism related to data dependencies? Data dependencies enforce order on instructions and thus remove instruction-level paral- lelism. 1d. (2 marks) Explain by giving reference to the pipelined implementation of the Y86 processor a very significant difference between RISC and CISC instruction set architectures. A RISC instruction set includes only operations that fit into the pipelined implementation well, so that excludes complicated instructions, in particular ones whose execution time is highly variable: block move instructions, instructions that reference memory multiple times, etc. 1e. (2 marks) What is data forwarding? Why is it useful? Allowing a early stage to access signals produced by a later stage. It is useful to handle data dependencies without stalling (or with less stalling) by allowing the decode stage to use results computed by instructions in execute and memory stages, even though they have not yet been written back to the register file. 2. (5 marks) HCL 2a. (3 marks) Give the HCL description of a single circuit that takes two 32-bit integer inputs, A and B, and computes a result OUT that evaluates to: 0 if either A or B is negative
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This note was uploaded on 10/09/2011 for the course CPSC 344 taught by Professor Karen during the Fall '10 term at The University of British Columbia.

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cs313-2006-t1-midterm2-solution - CPSC 313, 06w Term 1...

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