cs313-2006-t2-midterm2

cs313-2006-t2-midterm2 - CPSC 313, 06w Term 2 Midterm 2...

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CPSC 313, 06w Term 2— Midterm 2 Date: March 23, 2007; Instructor: Norm Hutchinson This is a closed book exam; no notes; you may use a calculator if you wish. Answer in the space provided; use the backs of pages if needed. There are 6 questions on 8 pages, totaling 50 marks. You have 50 minutes to complete the exam. On the last two pages you will find summaries of the Y86 instructions and stage outputs of the sequential processor implementation. You may find it profitable to (carefully) remove these pages from the exam. You should write this exam in pen - I will not consider requests to regrade solutions that are written in pencil. NAME: STUDENT NUMBER: SIGNATURE: SCORE: / 50 1. (12 marks) Short answers. 1a. (2 marks) Describe the difference between stalling and creating a bubble. 1b. (2 marks) Is it possible to stall the pipeline without creating a bubble? Explain briefly. 1c. (2 marks) What is the difference between a dependency and a hazard?
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1d. (2 marks) Give one example of an X86 (IA32) instruction that we have talked about in class that is impossible to execute on the pipelined processor described in class (PIPE-). Explain why it cannot be executed by PIPE-. 1e. (2 marks) What is branch prediction? Why is it useful? 1f. (2 marks) What is the single most significant advantage of a pipelined processor implementation over a sequential implementation? 2. (6 marks) RISC vs. CISC Each of the following statements is significantly more true of either a RISC or CISC instruction set archi- tecture. Write “RISC” or “CISC” in the blank before each statement to indicate which.
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This note was uploaded on 10/09/2011 for the course CPSC 344 taught by Professor Karen during the Fall '10 term at UBC.

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cs313-2006-t2-midterm2 - CPSC 313, 06w Term 2 Midterm 2...

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