cs313-2006-t2-problemset7 - CPSC 313, Winter 2006 - Term 2...

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CPSC 313, Winter 2006 - Term 2 Pipelining Assigned: March 9, Due: Sunday, March 18, 11:59PM All of these questions are to be handed in on paper. 1. Consider a five-stage pipeline with stage gate delays of 150 ps, 75 ps, 100 ps, 100 ps and 175 ps and a memory delay of 10 ps, as shown below. Signals flow from left to right. 150 10 10 175 100 10 100 10 75 10 (a) What is the maximum clock frequency this circuit could tolerate, measured in cycles per second? (b) What is best throughput this circuit could produce, measured in instructions-completed per sec- ond? (c) What is the execution latency of a single instruction, measured in seconds per instruction? (d) Answer questions a-c for a similar circuit that is not pipelined (i.e., where each stage is connected back-to-back with no intervening memory, as shown below)? 75 175 150 100 100 1
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(e) Suppose that in order to improve the throughput of the pipeline you could split a single stage into two equal sized stages. Which stage would you split to maximize the throughput improvement?
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This note was uploaded on 10/09/2011 for the course CPSC 344 taught by Professor Karen during the Fall '10 term at The University of British Columbia.

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cs313-2006-t2-problemset7 - CPSC 313, Winter 2006 - Term 2...

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