demo_11 - 6.002 Demo#11, 11A, 11B ( Load Set up...

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6.002 Demo#11, 11A, 11B ( Load Set up demo#11.set): ( Load Set up demo#11A.set): ( Load Set up demo#11B.set) Gate Delay Agarwal Fall 00 Lectures 12 and 13 Purpose: This demo examines gate delay using two cascaded MOSFET inverters, and also an RC circuit model. A square-wave input is applied to the first inverter, and the three relevant waveforms (input, middle, output) are shown on the scope. By increasing the frequency of the input, the gate delay becomes more pronounced (relative to the square wave period). The middle waveform exhibits the usual decaying exponential response, resulting in a delayed reaction by the second inverter. The second portion of this demo shows the response of an RC (LPF) circuit to a square wave input. This is used to motivate and justify the gate-to-source capacitance model of the MOSFET. Steps: 1. With the square-wave input to the cascaded inverters set to a low frequency (100 Hz), observe the input, the middle waveform (between the two inverters) and the output on the scope. Note that the signals are all
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demo_11 - 6.002 Demo#11, 11A, 11B ( Load Set up...

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