Oxide_thesis - STRESS-INDUCED LEAKAGE CURRENT IN DUAL-GATE...

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STRESS-INDUCED LEAKAGE CURRENT IN DUAL-GATE CMOSFETS WITH THIN NITRIDED GATE OXIDES HUANG JINSHENG ( B. Sc, PKU ) A THESIS SUBMITTED FOR THE DEGREE OF MASTER OF ENGINEERING DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING NATIONAL UNIVERSITY OF SINGAPORE 2004
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i ACKNOWLEDGEMENTS I would like to express my deepest thanks to my supervisors, Professor Ling Chung Ho and Dr Ang Diing Shemp, for their guidance, support and trust in the past three years, without which it would be impossible for me to complete this thesis. My gratitude must also go to Madam Ah Lian Kiat, my ex-colleague in the MOS Device Lab. Her knowledge and experience in the facilities as well as her kindness made the lab an excellent place to work in. Sincerely, I would like to extend my gratitude to Mr. Lun Zhao, Xia Jinghua, Tan Swee Tian and Timothy Phua and others, for all the help in one way or another during the days in MOS Device Lab. I would like to say “thank you” to all the friends I met in Singapore in the past three years, without whom the life here would have never been such a wonderful one. Last but not least, my gratitude goes to the most important persons in my life, my parents, my sisters, my brother and my wife, Yanping. Their understanding, patience, and support have carried me through all the difficult times. I feel so blessed to live in this family. H u a n g J i n s h e n g
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ii Table of Contents Acknowledgements i Table of Contents ii Summary v List of Figures vii List of Symbols xii Nomenclatures xiv Chapter One. Introduction and Literature Survey 1.1 Gate Oxide Scaling and Reliability 1 1.2 Intrinsic Leakage Currents in Gate Oxides 3 1.3 Stress-Induced Leakage Currents in Gate Oxides 5 1.3.1 General Physical Characteristics of SILC 6 1.3.2 Major Physical Models of SILC 9 1.3.3 Stress-Induced Traps in Oxides 15 1.3.4 Recent Advances of SILC 17 1.4 SILC and Oxide Degradation in Scaled Gate Oxides 19 1.5 Motivation of This Work 21 1.6 Organization of Thesis 22 R e f e r e n c e s 2 3
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iii Chapter Two. Experiment Techniques 2.1 Device Preparation 36 2.2 Major Experimental Procedures 36 2.2.1 Carrier Separation Technique 37 2.2.2 Constant Voltage Stress 42 2.2.3 Substrate Hot Carrier Injection 43 2.3 Summary 44 R e f e r e n c e s 4 5 Chapter Three. SILC in p+/pMOSFET with Ultrathin Nitrided Gate Oxides 3.1 Introduction 46 3.2 Electrons and Holes in the Gate Leakage Current 47 3.3 Gate SILC in p+/pMOSFETs 51 3.4 Hole SILC 55 3.5 Hole SILC vs. Electron SILC 58 3.6 Physical Model of Hole-Dominant SILC 62 3.7 Summary 69 R e f e r e n c e s 7 0 Chapter Four. SILC in n+/nMOSFET with Ultrathin Nitrided Gate Oxides 4.1 Introduction 72 4.2 Gate Leakage Currents in Virgin n+/nMOSFETs 73 4.3 SILC in n+/nMOSFETs 73
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iv 4.4 Summary 81 R e f e r e n c e s 8 2 Chapter Five. Degradation of Ultrathin Nitrided Gate Oxides 5.1 Introduction 83 5.2 Gate Stress Current and Gate Sense Current 83 5.3 SILC Generation and Oxide Degradation 85 5.4 Driving Force of Oxide Degradation 90 5.5 Summary 91 R e f e r e n c e s 9 2 Chapter Six. Conclusions and Future Work 6.1 Conclusions 93 6.2 Future Work 94
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v SUMMARY
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This note was uploaded on 10/12/2011 for the course ECON 32 taught by Professor Jj during the Spring '10 term at Alexandria University.

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Oxide_thesis - STRESS-INDUCED LEAKAGE CURRENT IN DUAL-GATE...

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