Thesis_Good - Subthreshold Leakage Control Techniques for...

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Unformatted text preview: Subthreshold Leakage Control Techniques for Low Power Digital Circuits by James T. Kao B.S. in Electrical Engineering and Computer Science, University of California at Berkeley (1993) S.M. in Electrical Engineering and Computer Science, Massachusetts Institute of Technology (1995) Submitted to the Department of Electrical Engineering and Computer Science in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Electrical Engineering and Computer Science at the MASSACHUSETTS INSTITUTE OF TECHNOLOGY May 2001 © Massachusetts Institute of Technology, 2001. All rights reserved. Author Department of Electrical Engineering and Computer Science May 30, 2001 Certified by Anantha P. Chandrakasan Associate Professor of Electrical Engineering Thesis Supervisor Accepted by Arthur C. Smith Chairman, Department Committee on Graduate Students Subthreshold Leakage Control Techniques for Low Power Digital Circuits by James T. Kao Submitted to the Department of Electrical Engineering and Computer Science on May 30, 2001, in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Electrical Engineering and Computer Science Abstract Scaling and power reduction trends in future technologies will cause subthreshold leakage currents to become an increasingly large component of total power dissipation. As a result, new techniques are needed in order to provide high performance and low power cir-cuit operation. This dissertation develops new circuit techniques that exploit dual thresh-old voltages and body biasing in order to reduce subthreshold leakage currents in both standby and active modes. To address standby leakage currents, a novel sleep transistor sizing methodology for MTCMOS circuits was developed and new “imbedded” dual V t techniques were described that could provide better performance and less area overhead by exploiting different logic styles. Work was also done to develop new MTCMOS sequential circuits, which include a completely novel way to hold state during standby modes. Body biasing circuit techniques were also explored to provide dynamic tuning of device threshold voltages to tune out parameter and temperature variations during the active state. This not only helps reduce active leakage currents but also improves process yields as well. A final research direction explored optimal V CC /V t tuning during the active modes as a function of varying workloads and temperatures so that a chip can auto-matically be configured to operate at the lowest energy level that balances subthreshold leakage power and dynamic switching power. Through novel circuit techniques and meth-odologies, this work illustrates how subthreshold leakage currents can be controlled from a circuit perspective, thereby helping to enable continued aggressive scaling of semicon-ductor technologies....
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Thesis_Good - Subthreshold Leakage Control Techniques for...

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