Sage_Journal - Proceedings of the Institution of Mechanical...

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http://pin.sagepub.com/ and Nanosystems Engineers, Part N: Journal of Nanoengineering Proceedings of the Institution of Mechanical http://pin.sagepub.com/content/223/1/19 The online version of this article can be found at: DOI: 10.1243/17403499JNN159 19 2009 223: Proceedings of the Institution of Mechanical Engineers, Part N: Journal of Nanoengineering and Nanosystems G Joshi, M Singh and M Chauhan and high-K gate dielectrics 2 (MOSFETs) with SiO semiconductor field effect transistors -- oxide -- Analysis of gate tunnelling currents in nanoscale metal Published by: http://www.sagepublications.com On behalf of: Institution of Mechanical Engineers can be found at: Nanosystems Proceedings of the Institution of Mechanical Engineers, Part N: Journal of Nanoengineering and Additional services and information for http://pin.sagepub.com/cgi/alerts Email Alerts: http://pin.sagepub.com/subscriptions Subscriptions: http://www.sagepub.com/journalsReprints.nav Reprints: http://www.sagepub.com/journalsPermissions.nav Permissions: http://pin.sagepub.com/content/223/1/19.refs.html Citations: by guest on September 5, 2011 pin.sagepub.com Downloaded from
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Analysis of gate tunnelling currents in nanoscale metal–oxide–semiconductor field effect transistors (MOSFETs) with SiO 2 and high-K gate dielectrics G Joshi*, M Singh, and M Chauhan UIET, Punjab University, Chandigarh, India The manuscript was received on 18 August 2009 and was accepted after revision for publication on 30 November 2009. DOI: 10.1243/17403499JNN159 Abstract: In this paper, an analytical model for gate tunnelling current has been deployed by solving the Schr odinger equation using the Wentzel–Kramer–Brillouin approximation method for a trapezoidal potential barrier. The gate tunnelling current has been computed for direct tunnelling from channel to gate as well as for tunnelling from source drain extension region to gate. The effect of temperature variation on gate tunnelling current with an SiO 2 thickness of 4 nm down to 1 nm has been studied at various gate voltages. Gate tunnelling in the case of high-K gate dielectrics and high-K stacks has also been analysed. In order to study the effect of temperature on gate tunnelling current in SiO 2 and in high-K dielectrics, the related parameters have been modelled based on physics. The effect of variation of substrate doping concentration (Na) on gate tunnelling current in an n-type metal–oxide–semiconductor field effect transistor (n-MOSFET) with SiO 2 has also been studied These studies have been used to bring out the design margins available in equivalent oxide thickness and Na. Keywords: Gate tunnelling current, high-K, temperature variations, source drain extension 1 INTRODUCTION Metal–oxide–semiconductor field effect transistor (MOSFET) scaling below a 100nm channel length regime is becoming increasingly limited by gate tun- nelling current, specifically with SiO 2 gate dielectrics.
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Sage_Journal - Proceedings of the Institution of Mechanical...

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