GATE OXIDE AND HIGH-K DIELECTRICS

GATE OXIDE AND HIGH-K DIELECTRICS - RELIABILITY MODELING OF...

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Unformatted text preview: RELIABILITY MODELING OF ULTRA-THIN GATE OXIDE AND HIGH-K DIELECTRICS FOR NANO-SCALE CMOS DEVICES LOH WEI YIP B. Eng (Hons), NUS A THESIS SUBMITTED FOR THE DEGREE OF DOCTOR OF PHILOSOPHY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING NATIONAL UNIVERSITY OF SINGAPORE 2004 Acknowledgments First and foremost, my deepest gratitude to my supervisors, Associate Professor Cho Byung Jin and Professor Li Ming Fu, who have given me guidance throughout my study in NUS. In particular, it is Assoc. Prof. Cho who have aspired me to reach for the highest standard in my researches and who have tirelessly reviewed and guided me in all my publications. It is with his help that I am able to produce credible results in the area of oxide and high-K reliability. Gratitude also goes to Prof. Li, who because of his insight and theoretical expertise is able to guide me to seek for a more theoretical understanding in all my researches. Without Assoc. Prof. Cho and Prof. Lis kind and patient guidance, it would be difficult for me to have completed this thesis. The advices and guidance of other teaching staffs are also gratefully acknowledged. In particular, Prof. Kwong DL, Assoc. Prof. Yoo WJ, Dr. Zhu CX, Dr Lee SJ, Dr. Yeo YC and Mr. Joo MS, have all given me tremendous help, advices and encouragements. I also wish to express my sincere gratitude to my fellow students in Silicon Nano Device Lab. (SNDL) and Center for Integrated Circuits Failure Analysis and Reliability (CICFAR) who have make my stay in NUS a joyful and meaningful experience. In particular, it is most gratifying to have the support and friendship of Mr. Kim Sun Jung who has so willing lend a helpful hand in all my experiments and Dr. Lim Peng Soon who has joined me in many fruitful discussions in both work and social matters. Thanks also go to all my friends including Wu Nan, Ren Chi, Tony Low, Chee Keong, Ng TH, Zerlinda, Tan KM, Chen JH, Wang YQ, Yu HY, Whang SJ, Park CS, and many others who have went out of their way to teach and assist me in this thesis. The support and assistance from all the staffs of SNDL and NUS is also gratefully acknowledged. In particular, Mr. Patrick Tang, Mr. Yong Yu Foo, Mr. Goh Thiam Pheng, Mrs. Ho Chiow Mooi, and Mr. Walter Lim have greatly assisted me in all manners of my administrative duties and experiments. Their kind assistances are greatly appreciated. Last but not least, I wish to dedicate this thesis to my parents, sister, Sook Fen and Gabriel and my dearest Tze Chieg. Without their emotional support, care and concerns, and continuous support and love, I would not have the privilege to even embark on this journey of my life. Summary As complementary metal-oxide semiconductor (CMOS) technology advances, the dimensions of its various key device components are scaled downward, from its present day micrometer range and eventually, to its ultimate limit - the nanometer regime. In this aspect, silicon dioxide (SiO 2 ), which forms the gate insulator for the transistor, is progressively reduced from thick to thin oxide (< 20 ), ultra-thin (<15...
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This note was uploaded on 10/12/2011 for the course ECON 32 taught by Professor Jj during the Spring '10 term at Alexandria University.

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GATE OXIDE AND HIGH-K DIELECTRICS - RELIABILITY MODELING OF...

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