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_ Grove calls leakage chip designers' top problem

_ Grove calls leakage chip designers' top problem - | Grove...

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Unformatted text preview: | Grove calls leakage chip designers' top problem 1 of 2 http://www.eetimes.com/electronics-news/4043995/Grove-calls-leakag... Welcome: [email protected] EE Times Home > News and Analysis News & Analysis Like 0 Grove calls leakage chip designers' top problem David Lammers 12/13/2002 4:20 PM EST Grove calls leakage chip designers' top problem SAN FRANCISCO — Power consumption, particularly off-state current leakage, is the major technical problem facing the semiconductor industry, said Andrew Grove, chairman of the board at Int In a luncheon address at the International Electron Devices Meeting (IED as chip densities increase to a billion transistors or more, power is "beco integration." While high-k dielectrics and clever circuit design may help keep the indu curve of doubling device densities every two to three years, those solutio steam by the end of this decade. Then, designers will have to make mor transistors, keeping within a certain power budget. Indeed, the pursuit of scalable new transistors is turning into a cat-herdin the researchers involved. In the attempt to control the short-channel effec performance, researchers have been producing thinner and thinner chan Devouring monster But with the much thinner channel comes really horrible leakage current, already threatened to devour ordinary bulk silicon designs at 130-nanom In an effort to reduce the leakage, one approach is to surround the chann even three sides. Most commonly this is done with a FinFET structure, in transistor becomes a tall, narrow bar of silicon sticking up into the surrou area that will be the channel is stripped, coated with a very thin gate diel with gate material — either all the way around, in which case the channe sides, or just on the vertical walls, in which case it is a double-gate devic better control over off-current. But that leaves the problem of threshold voltage. Today, the threshold vo channel region to establish a particular potential level relative to the poly Unfortunately, in very thin-channel devices, two things go wrong with tha difficult to control the uniformity of the dopants in the thin-channel film — difficult to fit them in in sufficient quantities. And the dopant atoms thems mobility in the channel. Hence, researchers are looking at alternatives that leave the channel eith intrinsic. That means that something has to be done about the work func At the moment there appear to be three schools of thought: First, leave th device geometry to solve the problem, as advocated by Taiwan Semicond The second school, currently the majority, suggests using a carefully form which various metals have been alloyed with the silicon. The third schoo metal gates of various types. Both of the last two factions control the gate 17-08-2011 09:29 | Grove calls leakage chip designers' top problem 2 of 2 http://www.eetimes.com/electronics-news/4043995/Grove-calls-leakag... manipulating the gate composition. Gate oxide must go Finally, there is the problem of gate dielectric material. Here the number explored is astonishing: The only apparent consensus is that sooner or la oxide will have to go. The problem is that with shrinking dimensions, the becoming so thin that tunneling current is becoming a major factor in ove creating yet another undesirable leakage path. So researchers are lookin either as barrier layers in combination with the gate dielectric or in place tunneling current. At the same time, higher-k materials are being sought control over the channel. Not only are large numbers of geometries and materials being explored, explored in various combinations. And once a research project settles on transistor type, channel thickness, dielectric material and thickness, and process implications of the combination have to be worked out. There's a lot of work to be done — much more than might be suggested stories in the IEDM papers presented here last week. More EE Times EE Times Network Subscriptions Sitemap EE Times Asia Newsletters About Us EE Times-China Editorial Calendar Privacy Policy EE Times-India Reprints EE Times Career Center EE Times Europe RSS Feeds Contact Us EE Times Japan Media Kit Email: f [email protected] [email protected] EE Times Korea EE Times Taiwan Electronic Supply & Manufacturing China Microwave Engineering Europe MCAD Online TechOnline India All materials on this site copyright ©2011 UBM Electronics, A UBM company All rights reserved DeepChip.com Design & Reuse 17-08-2011 09:29 ...
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