modeling_of_nanoscale_mosfets_thesis

modeling_of_nanoscale_mosfets_thesis - MODELING OF...

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MODELING OF NANOSCALE MOSFETS A DISSERTATION SUBMITTED TO THE DEPARTMENT OF ELECTRICAL ENGINEERING AND THE COMMITTEE ON GRADUATE STUDIES OF STANFORD UNIVERSITY IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY Changhoon Choi April 2002
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c Copyright by Changhoon Choi 2002 All Rights Reserved ii
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I certify that I have read this dissertation and that in my opinion it is fully adequate, in scope and in quality, as a dissertation for the degree of Doctor of Philosophy. Robert W. Dutton (Principal Advisor) I certify that I have read this dissertation and that in my opinion it is fully adequate, in scope and in quality, as a dissertation for the degree of Doctor of Philosophy. Krishna Saraswat (Associate Advisor) I certify that I have read this dissertation and that in my opinion it is fully adequate, in scope and in quality, as a dissertation for the degree of Doctor of Philosophy. Zhiping Yu Approved for the University Committee on Graduate Studies: iii
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Abstract As CMOS technology dimensions are being aggressively scaled to reach a limit where de- vice performance must be assessed against fundamental limits, nanoscale device modeling is needed to provide innovative new MOS devices as well as to understand the limits of the scaling process. This thesis describes advanced modeling of nanoscale MOSFETs from the viewpoint of device physics, which consists of three parts – gate, source/drain, and chan- nel modeling. In the gate modeling part, MOS C–V characteristics of gate oxide in the sub 2.0 nm region are modeled with an empirical, hybrid formulation for QM corrections implemented in a 2D device simulator. The sharp decrease in capacitance for gate oxides below 2.0 nm is modeled by using a distributed RC network that includes the gate tunneling current which is calculated using a Green’s function solver. Conversely, a reconstruction technique to extract the intrinsic gate capacitance, based on distorted curves in high leakage dielectric MOSFETs has been developed. An accurate direct tunneling model for circuit simulation is developed that incorporates an explicit surface potential model and quantum-mechanical corrections. In addition, CMOS circuit robustness in the presence of gate tunneling currents has been studied using circuit simulation, combined with a macro- circuit model of gate tunneling current and analytic estimation of the effects. Based on the simulation study, expected values of oxide thickness, needed to ensure the off-state gate leakage requirement of the ITRS roadmap, are outlined. The source and drain modeling part describes parasitic resistance issues of the source v
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and drain regions in the presence of very shallow junction depths. It addresses accurate modeling of the extrinsic resistance and application in the modeling of ultra-shallow junc- tion MOSFETs in order to optimize device performance. Analysis and optimization of device performance for an experimental process technology called Laser Thermal Process (LTP) are also discussed.
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This note was uploaded on 10/12/2011 for the course ECON 32 taught by Professor Jj during the Spring '10 term at Alexandria University.

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modeling_of_nanoscale_mosfets_thesis - MODELING OF...

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