Unformatted text preview: N and both PMOS has the width of W P . The only capacitance in this circuit is the loading capacitance C L . a. Compare two switching cases: (a) Input A switches from 0 to 1; (b) Input B switches from 0 to 1. Do they have the same output switching? Do they have the same delay? If not, which one is slower? Use the switch model to explain why. b. Assume the NMOS is modeled as a resistor (when it is on) with R N =10k · μ m and W N =1 μ m. The PMOS has R P =20k · μ m. C L =100fF. V DD =2.5V. What’s the 50% V DD delay for A switching from 0 to 1? c. Under the same condition as in b, find the size of PMOS, W P , so that the switching of A from 1 to 0 has the same delay as it switches from 0 to 1. For the 1 to 0 switching of A and B, do they have the same delay?...
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- Fall '11
- Logic gate, right figure, loading capacitance CL, static logic gate