Homework-01

Homework-01 - N and both PMOS has the width of W P The only...

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X A V DD PUN B D C S A B B A C L Out V DD EEE 425/591, ASU Fall 2011, Yu (Kevin) Cao Homework #1 Due Tuesday, September 6th, 10:30am, submitted to me in class. The objective of this homework is to practice (1) the construction of digital logic in CMOS technology, and (2) the basic concept of timing. 1. CMOS implementation Draw the circuit schematics to show the CMOS realization of the following functions: (a) Exclusive OR: b a b a f , i.e., b a f (b) Exclusive NOR: b a ab f , i.e., b a f 2. Logic construction Consider such a static logic gate as shown in the right figure. a. What is the logic function of X? b. Using A, B, C, D, and S as the inputs, design the pull-up network (PUN) with PMOS only. Try to minimize the number of PMOS you need. 3. Worst-case switching and basic sizing The right figure shows a NAND gate. Both NMOS has the width of W
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Unformatted text preview: N and both PMOS has the width of W P . The only capacitance in this circuit is the loading capacitance C L . a. Compare two switching cases: (a) Input A switches from 0 to 1; (b) Input B switches from 0 to 1. Do they have the same output switching? Do they have the same delay? If not, which one is slower? Use the switch model to explain why. b. Assume the NMOS is modeled as a resistor (when it is on) with R N =10k · μ m and W N =1 μ m. The PMOS has R P =20k · μ m. C L =100fF. V DD =2.5V. What’s the 50% V DD delay for A switching from 0 to 1? c. Under the same condition as in b, find the size of PMOS, W P , so that the switching of A from 1 to 0 has the same delay as it switches from 0 to 1. For the 1 to 0 switching of A and B, do they have the same delay?...
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This note was uploaded on 10/14/2011 for the course EE 591 taught by Professor Yucao during the Fall '11 term at ASU.

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