L5 Digital Logic Review - Topic 5 Review of Digital Logic...

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Review of Digital Logic Topic 5
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Digital System Building Blocks ± Multiplexer (MUX) ± Decoder ± ALU ± Register ± Register File ± Counter ± Controller (Finite State Machine) ± Tri-State Buffer ± Memory
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2-to-1-Line Multiplexer (Mux) A B Sel F Mux 0 1
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Quad 2-to-1-Line MUX A B sel F Mux 4 4 4 Mux Mux Mux Mux A2 B2 A1 B1 A0 B0 A3 B3 0 1 0 1 0 1 0 1 0 1 F0 F1 F2 F3 sel
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4-to-1-Line Multiplexer ± Selects one as output from 4 inputs, needs two select signals (4 = 2 2 ) 0 1 2 3 I 0 I 1 I 2 I 3 S 1 S 0 F Mux
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3×8 Decoder 2 2 2 1 2 0 0 1 2 3 4 5 6 7 A B C D0 D1 D2 D3 D4 D5 D6 D7 3×8 Decoder
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Truth Table of 3 × 8 Decoder 1 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 C B A Outputs Inputs ± For any input combination, only one of the outputs is turned on
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Arithmetic Logic Unit (ALU)
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Arithmetic Logic Unit (ALU) ± One-bit of ALU
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ALU
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Register File ± A bank of registers
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Register File – Read Operation ± Reading register file
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Register File – Write Operation ± Writing register file
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L5 Digital Logic Review - Topic 5 Review of Digital Logic...

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