L6 Intro to VHDL - Topic 6 Introduction to VHDL Hardware...

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Introduction to VHDL Topic 6
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Hardware Description Language (HDL) ± An HDL is a language that describes the hardware of digital systems in a textual form ± Can describe digital system specified at different levels of abstraction ± There are many HDLs, two most popular IEEE standards: VHDL and Verilog HDL; other IEEE standards: SystemC, SystemVerilog,
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Hardware Description Language (HDL) ± What is HDL used for? ± Design specification ± Design documentation ± Simulation ± Synthesis ± Attraction (Attribute) ± most reliable design process, with minimum cost and TTM (time-to- market) ± Reduce fault penalty!
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VHDL V HISC Æ Very High Speed Integrated Circuit H ardware D escription L anguage
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VHDL ± Has overlaps with high level programming language (e.g. C, Pascal) such as for loop and reusable modules, but it is absolutely NOT another high level programming language ± Keep in mind that the goal is HARDWARE, HDL is another way to design circuit, not to write software!!!
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VHDL ± Two applications of VHDL two steps of digital circuit design by VHDL: ± Design & Verification: a simulator interprets the HDL description and produces readable outputs that predict how the hardware will behave before it is actually fabricated ± timing diagram ± graphic report ± textual report ± Logic synthesis: is a process of translating an HDL model into a list of digital components and their interconnections; ± the synthesis result is to be used to fabricate an integrated circuit or to lay out a PCB (printed circuit board) or to configure an FPGA
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VHDL Modeling Digital Circuit in1 in3 in2 out1 out2
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VHDL Modeling Digital Circuit in1 in3 in2 out1 out2 Entity Entity Declaration Architecture Description
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VHDL Modeling --this is a VHDL model of HA --this is an ENTITY declaration entity Half_Adder is port (A, B : in bit ; Sum, Carry: out bit ); end entity Half_Adder; --this is an ARCHITECTURE description architecture RTL of Half_Adder is begin Sum <= (A and ( not B)) or (( not A) and B); Carry <= A and B; end architecture RTL; Half Adder A B Carry Sum
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Entity Declaration entity Half_Adder is port (A, B: in bit ; Sum, Carry: out bit ); end Entity Half_Adder; keyword Mode (direction) I/O ports Entity name Data type
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Some VHDL Semantics ± VHDL is NOT case sensitive! ± Reserved keywords ± An entity declaration is enclosed by entity and end entity ± Entity name should be composed of alphabet letters, digits, and underscores, may not start with digits ± Entity declaration contains a port list including all the I/O ports ± Ports are declared with port mode: in , out , or others ± Ports are defined as type of bit , or others, type of bit may represent logic values ’0’ or ’1’
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Architecture Description architecture RTL of Half_Adder is begin Sum <= (A and ( not B)) or (( not A) and B); Carry <= A and B; end architecture RTL; keyword Entity name Architecture name Built-in logic functions Concurrent Signal Assignment (CSA) statement Signal assignment operator
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±
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L6 Intro to VHDL - Topic 6 Introduction to VHDL Hardware...

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