L7 Single Cycle Processor

L7 Single Cycle Processor - Single Cycle Processor Topic 7...

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Unformatted text preview: Single Cycle Processor Topic 7 Introduction ¡ MIPS implementations ¡ A simplified single-cycle version ¡ A more realistic pipelined version ¡ An FSM based multi-cycle version ¡ Support simple subset, shows most aspects of MIPS ¡ Memory reference: lw , sw ¡ Arithmetic/logical: add , sub , and , or , slt ¡ Control transfer: beq , j Instruction Execution ¡ PC → program memory, fetch instruction ¡ Register addresses to access register file, read registers ¡ Depending on instructions ¡ Use ALU/Adder to calculate ¡ Arithmetic/logic result ¡ Memory address for load/store ¡ Branch target address ¡ Access register or data memory for load/store ¡ Update PC ← target address or PC + 4 First View of CPU Combination of Controller and Datapath Clocking Methodology ¡ Combinational logic transforms data during clock cycles ¡ Between clock edges ¡ Input from state elements, output to state element ¡ Longest delay determines clock period Building a Datapath ¡ Datapath ¡ Elements that process data and addresses...
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This note was uploaded on 10/14/2011 for the course EE 270/370 taught by Professor Gangzheng during the Fall '11 term at Shanghai Jiao Tong University.

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L7 Single Cycle Processor - Single Cycle Processor Topic 7...

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