L8 Pipelined Processor - Topic 8 Pipelined Processor...

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Pipelined Processor Topic 8
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Performance Issues ± Longest delay determines clock period ± Critical path: load instruction ± Instruction memory register file ALU data memory register file ± Not feasible to vary period for different instructions ± Violates design principle ± Making the common case fast ± We will improve performance by pipelining
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Pipelining Analogy ± Pipelined laundry: overlapping execution ± Parallelism improves performance ± Four loads: ± Speedup = 8/3.5 = 2.3 ± Non-stop: ± Speedup = 2n/0.5n + 1.5 4 = number of stages
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MIPS Pipeline ± Five stages, one step per stage 1. IF: Instruction fetch from memory 2. 3. EX: Execute operation or calculate address 4. MEM: Access memory operand 5. WB: Write result back to register
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Pipeline Performance ± Assume time for stages is ± 100ps for register read or write ± 200ps for other stages ± Compare pipelined datapath with single-cycle datapath 500ps 200ps 100 ps
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L8 Pipelined Processor - Topic 8 Pipelined Processor...

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