L11+Exception - Topic 11 Hazards & Exceptions...

Info iconThis preview shows pages 1–5. Sign up to view the full content.

View Full Document Right Arrow Icon
– Exceptions Topic 11
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Exceptions and Interrupts ± “Unexpected” events require control flow to be altered ± Exception ± Arises within the CPU ± e.g., undefined opcode, overflow, syscall, … ± Interrupt ± From an external I/O controller ± Dealing with them without sacrificing performance is hard
Background image of page 2
Handling Exceptions ± Save PC of interrupted instruction ± In MIPS: Exception Program Counter (EPC), 32 bits ± Actually PC of the interrupted instruction + 4 ± Service the exception or interrupt according to the causes ± In MIPS: 32-bit Cause register and single entry point, usually 8000 0180 ± Or multiple entry points, each entry point for one cause – Vectored Interrupts ± Jump to handler at entry point
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Vectored Interrupts ± Vectored Interrupts ± Handler address determined by the cause ± Example: ± Undefined opcode: C000 0000 ± Overflow: C000 0020 ± …: C000 0040 ± MIPS: Entry points separated by 8 instructions ± Instructions either ± Deal with the interrupt if handler is small, or ± Jump to real handler if hander is bigger than 8 instructions
Background image of page 4
Image of page 5
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 10/14/2011 for the course EE 270/370 taught by Professor Gangzheng during the Fall '11 term at Shanghai Jiao Tong University.

Page1 / 15

L11+Exception - Topic 11 Hazards & Exceptions...

This preview shows document pages 1 - 5. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online