L12+Cache - Topic 12 Memory Hierarchy Cache Memory...

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Topic 12 Memory Hierarchy - Cache
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Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 2 Memory Technology ± Static RAM (SRAM) ± 0.5ns – 2.5ns, $2000 – $5000 per GB ± Dynamic RAM (DRAM) ± 50ns – 70ns, $20 – $75 per GB ± Magnetic disk ± 5ms – 20ms, $0.20 – $2 per GB ± Ideal memory ± Access time of SRAM ± Capacity and cost of disk
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Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 3 Principle of Locality ± Programs access a small proportion of their address space at any time ± Temporal locality ± Items accessed recently are likely to be accessed again soon ± e.g., instructions in a loop ± Spatial locality ± Items near those accessed recently are likely to be accessed soon ± E.g., sequential instruction access, array data
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Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 4 Memory Hierarchy Subset Subset
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Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 5 Taking Advantage of Locality ± If referenced ± Copy recently accessed (and nearby) items from disk to smaller DRAM memory ± Main memory ± Copy more recently accessed (and nearby) items from DRAM to smaller SRAM memory ± Cache memory attached to or inside CPU
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Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 6 Memory Hierarchy Levels ± Concepts: ± Block (aka line) ± unit of data referencing ± May be one or multiple words ± Hit ± If accessed data is present in upper level, access satisfied by upper level ± Hit ratio: hits/accesses ± Miss ± If accessed data is absent ± block copied from lower level ± Time taken: miss penalty ± Miss ratio: misses/accesses = 1 – hit ratio ± Then accessed data supplied from upper level
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Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 7 Hit Time and Miss Penalty ± Hit time ± Time to access a memory including ± Time to determine whether a hit or miss ± Time to pass block to requestor ± Miss penalty ± Time to fetch a block from lower level upon a miss including ± Time to access the block ± Time to transmit it between levels ± Time to overwrite the higher level block ± Time to pass block to requestor
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Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 8 Cache Memory ± Cache memory ± The level of the memory hierarchy closest to the CPU ± Example: assume a cache with 1-word blocks. X 1 , …, X n–1. Now CPU requests X n ± Miss: X n is brought in from lower level ± But ± How do we know if the data is present? ± Where do we look?
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Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 9 Direct Mapped Cache ± Location of a word in cache determined by address of the word ± Direct mapped: each memory location, one choice in cache ± (Block address) modulo (Number of blocks in cache) ± Direct mapped is an n-to-1 mapping ± Number of blocks is a power of 2 ± Use low-order address bits
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Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 10 Tags and Valid Bits ± How do we know which block in a cache location since it’s n-to-1 mapping? ± Store block address as well as the data
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L12+Cache - Topic 12 Memory Hierarchy Cache Memory...

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