L9+FSM+Optimizations

# L9+FSM+Optimizations - Lecture 9 FSM Optimizations Digital...

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1 Digital Design Copyright © 2006 Frank Vahid Lecture 9 FSM Optimizations

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2 Digital Design Copyright © 2006 Frank Vahid Moore vs. Mealy FSMs FSM implementation architecture – Next state logic – function of present state and FSM inputs – Output logic • Depends on present state only – Moore FSM • Depends on both present state and FSM inputs – Mealy FSM clk IO State register Combinational logic S N clk I O St at e r eg i st er Next-state logic Output logic FSM outputs inputs N S (a) I O St at e reg i st er Next-state logic Output logic N S (b) Mealy FSM a dds thi s Moore Mealy a
3 Digital Design Copyright © 2006 Frank Vahid Moore FSM Representation Input Present State Outputs In S1 S3 1 1 0 1 0 Out S2 S2 S1 S2 S0 S1 S3 N.S. S3 S2 S2 S1 S1 S0 S0 P.S. 0 1 0 1 0 1 0 State Diagram State Table

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4 Digital Design Copyright © 2006 Frank Vahid Mealy FSM Representation Inputs / Outputs Present State In 1 S1 S3 1 0 1 0 0 1 1 0 Out S3 S0 S2 S2 S1 S1 S0 N.S. S3 S2 S2 S1 S1 S0 S0 P.S. 0 1 0 1 0 1 0 State Table State Diagram
5 Digital Design Copyright © 2006 Frank Vahid Design of an FSM - Mealy Example: design a non-overlapping sequence detector as Mealy FSM Z is determined every three bits, Z = 1, as soon as an input sequence 101 is detected one input: X one output: Z detector 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 time 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 Z = 0 1 0 1 0 1 0 0 1 1 0 1 1 0 0 X =

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6 Digital Design Copyright © 2006 Frank Vahid Derivation of State Diagram • Drawing the state diagram A0 A1 A2 A3 successful path 1/0 0/0 1/1 A4 A5 A6 0/0 1,0/0 1,0/0 1/0 0/0 1/0 0/0 0/0 1/0
7 Digital Design Copyright © 2006 Frank Vahid State Reduction Two states are equivalent iff their next states and outputs are identical 0 0 A6 A6 A5 0 0 A1 A4 A6 0 0 A5 A5 A4 0 0 A1 A4 A3 1 0 A3 A6 A2 0 0 A5 A2 A1 0 0 A1 A4 A0 X = 1 X = 0 X = 1 X = 0 Output Next State Present State A0 equivalent states A0 A0 A0 Alternative representation of state table • Easier for state reduction • Harder for truth table

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8 Digital Design Copyright © 2006 Frank Vahid State Reduction Reduced state table 0 0 S0 S0 S4 0 0 S4 S4 S3 1 0 S0 S0 S2 0 0 S4 S2 S1 0 0 S1 S3 S0 X=1 X=0 X=1 X=0 Output Next State Present State A0 Æ S0 A1 Æ S1 A2 Æ S2 A4 Æ S3 A5 Æ S4 0 0 A0 A0 A5 0 0 A1 A4 A6 0 0 A5 A5 A4 0 0 A1 A4 A3 1 0 A0 A0 A2 0 0 A5 A2 A1 0 0 A1 A4 A0 X=1 X=0 X=1 X=0 Output Next State Present State
9 Digital Design Copyright © 2006 Frank Vahid State Reduction Reduced state diagram S0 S1 S2 successful path 1/0 0/0 1/1, 0/0 S3 S4 0/0 1,0/0 1,0/0 1/0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 time 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 Z = 0 1 0 1 0 1 0 0 1 1 0 1 1 0 0 X =

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10 Digital Design Copyright © 2006 Frank Vahid State Assignment Number of bits of binary number should be enough to represent all the states 0 0 000 000 100 0 0 100 100 011 1 0 000 000 010 0 0 100 010 001 0 0 001 011 000 X=1 X=0 X=1 X=0 Output Next State Present State 011 S3 001 S1 000 S0 010 S2 100 S4 Out Next State Present State In 0 0 0 1 1 1 0 1 0 1 0 0 0 0 0 0 0 Z 0 0 0 1 0 0 0 0 1 n0 0 0 0 0 0 0 0 1 1 n1 x 0 0 1 0 x 0 1 0 0 0 n2 …… 0 0 1 0 0 1 0 1 0 P0 0 1 0 0 0 1 1 0 0 P1 1 0 0 0 1 0 0 0 0 P2 1 1 1 1 …… 0 0 0 0 0 X
11 Digital Design Copyright © 2006 Frank Vahid Derivation of State and Output Equations X X X 0 11 X X X 0 01 0 1 01 0 0 11 0 0 10 0 1 00 10 00 X X X 0 11 X X X 0 01 1 0 01 1 1 11 0 0 10 0 0 00 10 00 X X X 0 11 X X X 0 01 0 0 01 0 0 11 1 0 10 0 0 00 10 00 X X X 0 11 X X X 0 01 0 0 01 0 0 11 0 1 10 0 1 00 10 00 X p2 p1p0

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L9+FSM+Optimizations - Lecture 9 FSM Optimizations Digital...

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