L10+Register+&+Shifter

L10+Register+&+Shifter - Lecture 10 Register &...

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1 Digital Design Copyright © 2006 Frank Vahid Lecture 10 Register & Shifter
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2 Digital Design Copyright © 2006 Frank Vahid Introduction Two major subsystems in typical digital system – Controller • Controllers generates signals to control datapath based on environment event or state – Datapath • Datapath routes data to particular destination device according to control signals generated by controller This chapter introduces numerous datapath components, and simple datapaths
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3 Digital Design Copyright © 2006 Frank Vahid Registers Can store data, very common in datapaths Basic register: Loaded every cycle – Useful for implementing FSM -- stores encoded state – For other uses, may want to load only on certain cycles Combinational logic State register s1 s0 n1 n0 x b clk I3 I2 I1 I0 Q3 Q2 Q1 Q0 reg(4) D Q D Q D Q D Q I2 I3 Q2 Q3 Q1 Q0 I1 I0 clk 4-bit register
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4 Digital Design Copyright © 2006 Frank Vahid Register with Parallel Load Add 2x1 mux to each flip-flop Register’s load input selects mux input to pass – Either existing flip-flop value, or new value to load load I3 I2 I1 I0 Q3 Q2 Q1 Q0 Synchronous active high Load
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5 Digital Design Copyright © 2006 Frank Vahid Register Example using the Load Input: Weight Sampler Scale has two displays – Present weight – Saved weight – Useful to compare present item with previous item Use register to store weight – Pressing button causes present weight to be stored in register • Register contents always displayed as “Saved weight,” even when new present weight appears Scale Saved weight Weight Sampler Present weight clk b Save I3 I2 I1 I0 Q3 Q2 Q1 Q0 load 3 pounds 0011 3 pounds 0010 2 pounds 1 a
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6 Digital Design Copyright © 2006 Frank Vahid Register Example: Above-Mirror Display C d0 d1 d2 d3 e i0 i0 i1 i2 i3 a0 a1 en i1 2 × 4 8 8 8 8 8 D d 8 xy s1 s0 8-bit 4 × 1 load load load load reg0 reg1 reg2 reg3 T A I M Four simultaneous values from car’s computer To reduce wires: Computer writes only 1 value at a time, loads into one of four registers 0 1 0001010 1 1 0001010 Loaded on clock edge
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7 Digital Design Copyright © 2006 Frank Vahid C d0 d1 d2 d3 e i0 i0 i1 i2 i3 a0 a1 load i1 2 × 4 8 8 8 8 8 D d 8 xy s1 s0 8-bit 4 × 1 load load load load reg0 reg1 reg2 reg3 T A I M Register Files MxN register file provides efficient access to M N-bit-wide registers – If we have many registers but only need access one or two at a time, a register file is more efficient – Ex: Above mirror display (earlier example), but this time having 16 32-bit registers • Too many wires, and big mux is too slow C d0 d15 e i0 i15 load i3-i0 4 × 16 32 32 32
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This note was uploaded on 10/14/2011 for the course EE 270/370 taught by Professor Gangzheng during the Fall '11 term at Shanghai Jiao Tong University.

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L10+Register+&+Shifter - Lecture 10 Register &...

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