L12+Timing+Issues - Lecture 12 Timing Issues 1 Outline...

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1 Lecture 12 Timing Issues
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2 Outline Timing requirements for FSM Setup time and hold time Asynchronous input and metastability Synchronizer Switch debouncing Clock skew Other timing parameters Hazards
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3 State Machine Finite State Machine Combinational Logic Inputs State Register Present State (PS) Outputs Feedback of present state Next State (NS) FSM Outputs
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4 Clocking Methodology for FSM • Combinational logic transforms data during clock cycles – Between clock edges • Clock cycles should be – Long enough to allow combinational logic completes computation • Longest delay determines clock period – Short enough to ensure acceptable performance and to capture small changes on external inputs
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5 Hardware Constraints – Setup and Hold An edge-triggered flip-flop will not operate correctly if the data is not stable for a sufficient time before and after the clock edge Storage element may be put in nondeterministic state Setup Time – Minimum time that data must be stable prior to the triggering edge Setup-time violations are cause by combinational paths that are long relative to the clock cycle Setup Time Clock
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6 Hardware Constraints – Setup and Hold Hold Time: – Minimum time that data must remain stable after the triggering edge Hold-time violations are caused by short paths that allow a signal to propagate from a source flip-flop to a destination flip-flop and change the data that was created in the previous cycle before the destination flip-flop has registered its output Setup and hold time: ns Hold interval Clock
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7 Metastability and Asynchronous Inputs If the setup or hold condition of an edge-triggered flip-flop is violated the flip-flop may enter a metastable state. In a fully synchronous system all circuits are driven by a common clock, and the state registers may change only under the control of the clock Synchronous system may be driven by asynchronous inputs which may put flip flops into the metastable state State_0 State_1 State_m Metastable state
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8 Asynchronous Inputs Examples: Keyboard activity, push buttons, and interrupts to a computer. Problems caused by asynchronous inputs – The unpredictable arrival of an asynchronous input may cause a setup condition to be violated.
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L12+Timing+Issues - Lecture 12 Timing Issues 1 Outline...

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