chap5 - ELEC151 Digital Circuits and Systems Lecture Note...

Info iconThis preview shows pages 1–3. Sign up to view the full content.

View Full Document Right Arrow Icon
ELEC151 Digital Circuits and Systems Ho-Chi Huang, Lecture Notes, No. 5-1 Lecture Note #5 Sequential Logic • Sequential circuits 5-1 – feedback and clock • Latches 5-2 – SR, D and JK latches • Flip-flops 5-3 – level-sensitive and edge trigger • State transition table and diagram (5-4) • State reduction and assignment (5-6) • Design procedure of sequential circuit (5-7) • HDL for sequential circuits (5-5) • Section 5-4~7 will be covered after Chapter 6 • Reading Assignments: – Section 5-1, 5-2, 5-3, ELEC151 Digital Circuits and Systems Ho-Chi Huang, Lecture Notes, No. 5-2 Combinational Circuit Outputs Inputs Next-state Combinational Circuit Output Combinational Circuit Finite States Inputs Outputs Feedbacks Clocks Combinational vs Sequential Logic • Combinational Logic – Outputs are solely determined by inputs – Represented by truth table • Sequential Logic – There are feedbacks feedbacks and clocks clocks – Outputs are determined by inputs and feedbacks at clocks – Represented by state-transition diagram or flow chart ELEC151 Digital Circuits and Systems Ho-Chi Huang, Lecture Notes, No. 5-3 Simple Circuit with Feedback • One inverter with feedback – Self-oscillation, 2 gate delays for one period – Odd-number of inverters with feedback » self-oscillation of 2x gate delays of one path • Two inverters with feedback – Memory element (or states) – Basis for commercial static RAM designs – Read-only, but has no write function • Memory with read/write capability – Selectively break the feedback path by transmission gates to load new value into the cell – A can be written to Z when LD = 1 » Write SW On & Feedback SW Off – Z holds the value when LD = 0 » Write SW Off & Feedback SW On "0" "1" “0?" "1" Z LD LD’ LD LD’ A ELEC151 Digital Circuits and Systems Ho-Chi Huang, Lecture Notes, No. 5-4 Basic SR Latch • Cross-coupled NOR gates – Inverters replaced by NOR gates – 2 inputs, 4 combinations » R=S=0 ==> 2-NOR = 1-NOT; Memory » R=1 R=1 , S=0 ==> Q = 0 Q = 0 , Q’ = 1; Reset »R=0 , S=1 ==> Q’ = 0 = 0 , Q = 1; Set » R=S=1 ==> Q =0, Q ’=0 =0 ?; Forbidden ? – Memory, set (write 1) and reset (write 0) functions – What happens if the inputs are changed from R=S=1 to R=S=0 ? » The Q and Q’ cannot be held like a memory, but start racing R S
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
ELEC151 Digital Circuits and Systems Ho-Chi Huang, Lecture Notes, No. 5-5 Basic S’R’ Latch • Cross-coupled NAND gates – Inverters replaced by NAND gates – 2 inputs, 4 combinations »R ’=S =1 ==> 2-NAND = 1-NOT; Memory =1, S’=0 =0 ==> Q = 1 , Q’ = 0; Set » R’=0 =0 , S’ =1 ==> Q’ = 1 = 1 , Q = 0; Reset » R’=S’=0 =0 ==> Q =1 , Q’=1 =1 ?; Forbidden ? – Memory, set (by S=0) and reset (by R=0) functions » NOR latch is more nature that S=1 sets Q and R=1 resets Q – The outputs race when R=S=0 are changed to R=S=1 R’ S’ S’ R’ S’ R’ ELEC151 Digital Circuits and Systems Ho-Chi Huang, Lecture Notes, No. 5-6 Gated SR Latch • Adds an input enable C to the basic SR latch – C = 1, S and R are inverted and passed to the basic NAND latch » R=S=0, Memory » R=1, S=0 Reset, Q=0
Background image of page 2
Image of page 3
This is the end of the preview. Sign up to access the rest of the document.

Page1 / 9

chap5 - ELEC151 Digital Circuits and Systems Lecture Note...

This preview shows document pages 1 - 3. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online