chap7 - ELEC151 Digital Circuits and Systems Ho-Chi Huang,...

Info iconThis preview shows pages 1–3. Sign up to view the full content.

View Full Document Right Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: ELEC151 Digital Circuits and Systems Ho-Chi Huang, Lecture Notes, No. 7-1 Lecture Note #7 Hardware Description Language • Hardware Description Language 3-9 – Design entry for logic simulation and synthesis – Two IEEE standards, and many others » V HDL used in PLD, (originated by DoD, more popular) • VHSIC Very High-Speed Integrated Circuits » Verilog HDL used in textbook, (developed by Cadence) • HDL for Combinational Circuits 4-11 – Boolean expressions – Half adders, decoders, multiplexers, ... • HDL for Registers and Counters 5-5, 6-6 – Sequential statements – Latches, flip-flops, registers and counters, • Reading Assignments: – Section 3-9, 4-11, 5-5, 6-6 ELEC151 Digital Circuits and Systems Ho-Chi Huang, Lecture Notes, No. 7-2 The Elements of Modern Design (from lecture note #1) Rapid Prototyping Technologies Design Representations Circuit Technologies TTL MOS CMOS BiCMOS Truth Tables Boolean Algebra Logic Gates Logic Blocks Behaviors Waveforms Simulation Synthesis ROM PAL PLA SPLD CPLD FPGA Computer-Aided Design Representations, Circuit Technologies, Rapid Prototyping ELEC151 Digital Circuits and Systems Ho-Chi Huang, Lecture Notes, No. 7-3 Representation of a Digital Design (from lecture note #1) BEGIN i1: inverter_gate PORT MAP (A, s1); i2: inverter_gate PORT MAP (B, s2); a1: and_gate PORT MAP (B, s1, s3); a2: and_gate PORT MAP (A, s2, s4); a3: and_gate PORT MAP (A, B, Carry) o1: or_gate PORT MAP (s3, s4, Sum); END structural; A SUM Carry s4 s3 a1 a2 a3 o1 i1 i2 s2 s1 B • Behaviors – Textual description of the netlist by hardware description language (HDL) ELEC151 Digital Circuits and Systems Ho-Chi Huang, Lecture Notes, No. 7-4 VHDL of a Half Adder -- A more completed description ENTITY half_adder IS PORT (A, B: IN STD_LOGIC; Sum, Carry: OUT STD_LOGIC); END half_adder; ARCHITECTURE structural OF half_adder IS COMPONENT inverter_gate PORT (A: IN STD_LOGIC, Z: OUT STD_LOGIC); END COMPONENT ; COMPONENT and_gate PORT (A, B: IN STD_LOGIC, Z: OUT STD_LOGIC); END COMPONENT ; COMPONENT or_gate PORT (A, B: IN STD_LOGIC, Z: OUT STD_LOGIC); END COMPONENT ; SIGNAL s1, s2, s3, s4: STD_LOGIC BEGIN i1: inverter_gate PORT MAP (A, s1); i2: inverter_gate PORT MAP (B, s2); a1: and_gate PORT MAP (B, s1, s3); a2: and_gate PORT MAP (A, s2, s4); a3: and_gate PORT MAP (A, B, Carry); o1: or_gate PORT MAP (s3, s4, Sum); END structural ; ELEC151 Digital Circuits and Systems Ho-Chi Huang, Lecture Notes, No. 7-5 VHDL of a Half Adder -- Inverter gate model-- inverter gate model -- ENTITY inverter_gate IS PORT (A: IN STD_LOGIC; Z: OUT STD_LOGIC); END inverter_gate; ARCHITECTURE data-flow OF inverter_gate IS BEGIN Z <= NOT A AFTER 10 ns; END data-flow ; • ENTITY and ARCHITECTURE are two main parts of a VHDL design – ENTITY declares the block diagram of a component » It consists of external inputs and outputs after PORT – ARCHITECTURE defines the internal operations » How the outputs are related to the inputs » There are different ARCHITECTURES for the same function...
View Full Document

This note was uploaded on 10/16/2011 for the course ELEC 308,315,10 taught by Professor Prof.shenghuisong during the Spring '11 term at CUHK.

Page1 / 8

chap7 - ELEC151 Digital Circuits and Systems Ho-Chi Huang,...

This preview shows document pages 1 - 3. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online