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# chap8 - ELEC151 Digital Circuits and Systems Lecture Note#8...

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ELEC151 Digital Circuits and Systems Ho-Chi Huang, Lecture Notes, No. 8-1 Lecture Note #8 Finite State Machine Analysis of sequential circuit 5-4 – Mealy and Moore machine – Reverse engineering » From schematics to state-transition diagram Design of sequential circuit 5-7 – Design procedure » 7 steps from specifications to the schematics State reduction and assignment 5-6 – Two most important design steps Reading Assignments: – Section 5-4, 5-6, 5-7 ELEC151 Digital Circuits and Systems Ho-Chi Huang, Lecture Notes, No. 8-2 Finite State Machine and Sequential Logic Sequential logic and Finite-state machine (FSM) – FSM is a more general term of sequential logic Storage register – Multiple flip-flops (finite states) in parallel – No next-state and output logic Shift register – Multiple flip-flops (finite states) in series – Might or might not have next-state and output logic Conversion of flip-flop – One flip-flop, one next-state logic, no output logic Next-state Combinational Circuit Output Combinational Circuit Finite States Inputs Outputs Feedbacks Clocks ELEC151 Digital Circuits and Systems Ho-Chi Huang, Lecture Notes, No. 8-3 Finite-state Machine and Counters Next-state Combinational Circuit Finite States Outputs = states Feedbacks Clocks Counter has no output logic – The current states are the outputs – Johnson and ring counters have even no next-state logic Counter has no data inputs, but only clock input – Proceed through a well-defined sequence of states – No data input to alter the sequence of states Design of counter – Selection of flip-flops – Design of next-state logic ELEC151 Digital Circuits and Systems Ho-Chi Huang, Lecture Notes, No. 8-4 Counter Design Procedure Understand the problem – State-transition diagram and table (States are outputs) Selection of flip-flops – T, D and JK flip-flops Design of next-state logic – Truth table » inputs are current states (no data inputs) » outputs are inputs to the flip-flops » derived by excitation table (no output logic) • Implementation – Gate counts

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ELEC151 Digital Circuits and Systems Ho-Chi Huang, Lecture Notes, No. 8-5 FSM Design Procedure Understand the problem – State-transition diagram and table Number of states could be reduced (State Reduction) – few states imply few flip-flops Assign binary values to states (State Assignment) – can lead to few gate count in next-state and output logic Selection of flip-flops – T, D and JK flip-flops Design of next-state logic – inputs are current states and data inputs – outputs are inputs to the flip-flops Design of output logic – Truth table is available for the specifications • Implementation ELEC151 Digital Circuits and Systems Ho-Chi Huang, Lecture Notes, No. 8-6 6 Basic Design Steps of FSM • 1. Understand the statement of the Specification – With a block diagram • 2. Obtain an abstract specification of the FSM
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chap8 - ELEC151 Digital Circuits and Systems Lecture Note#8...

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