351_quiz6_s - if-then-else syntax instead of a case syntax?...

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ECE 351 Quiz #6 Each question is worth 2 points 1. What is IP (in the context of HDL programs)? Reusable modules of functionality. In other words, any Verilog module is IP. 2. What is the best way to synthesize memory in FPGAs? Use memory primitives (IP) furnished by the FPGA vendor. 3. What is latch inference ? Undesirable latches in the synthesized design caused by poor syntax. In other words, the “poor syntax” INFERS that latches should be in the design---even when they are not necessary. 4. When it is better to use an
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Unformatted text preview: if-then-else syntax instead of a case syntax? Use If-then-else when the number of choices are 2 or less. Otherwise use the case statement. 5. The SPARTAN-6 FPGA CLBs just like all other FPGAs. But it also contains several blocks of special purpose circuitry. What is one of them? Any one of the following is acceptable • DSP slices (will accept multipler/adder/accumulate circuitry) • Memory controller blocks • Endpoint blocks for PCI express • Serial transceivers...
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This note was uploaded on 10/16/2011 for the course ECE 351 taught by Professor Greenwood during the Spring '11 term at Portland State.

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