Unformatted text preview: the testbench to find out how construct the port list in your module.) You must simulate your design and turn in a copy of your Verilog source code and a hardcopy of the timing diagram produced by the simulator. (No timing diagram, no credit.)...
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This note was uploaded on 10/16/2011 for the course ECE 351 taught by Professor Greenwood during the Spring '11 term at Portland State.
- Spring '11