351_hw5a - 3. the encoder produces the correct output if 4...

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ECE HW#4 You are to design and simulate a priority encoder in Verilog. (You can find the datasheet here .) Write a testbench that will verify 1. the encoder produces the correct output when one (and only one) input is asserted. Be sure the testbench checks all inputs. 2. the encoder produces the correct output if 2 inputs are asserted. (Use inputs I3 and I7 for this test.)
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Unformatted text preview: 3. the encoder produces the correct output if 4 inputs are asserted. (Use any 4 inputs of your choice.) 4. repeat (3), except assert the other 5 inputs instead. You must turn in the code for your encoder, the code for your testbench, and the timing diagram of the simulation....
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