lectureweek5_1

lectureweek5_1 - Computer Architecture CSC/CPE 315...

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Unformatted text preview: Computer Architecture CSC/CPE 315 Pipelining Winter 2010 Instructor: Joe Grimes TA: Stephen Beard Todays Goals Why MIPS is good for pipelining. Pipeline overhead fill cost Know hazards Know why hazards are problematic Start finding solutions to hazards Graphically Representing Pipelines Can help with answering questions like:- how many cycles does it take to execute this code?- what is the ALU doing during cycle 4?- use this representation to help understand datapaths Conventional Pipelined Execution Representation IFetch Dcd Exec Mem WB IFetch Dcd Exec Mem WB IFetch Dcd Exec Mem WB IFetch Dcd Exec Mem WB IFetch Dcd Exec Mem WB IFetch Dcd Exec Mem WB Program Flow Time Why Pipeline? Suppose we execute 100 instructions. How long on each architecture? Single Cycle Machine- 4.5 ns/cycle, CPI=1 Ideal pipelined machine- 1.0 ns/cycle, CPI=1 (but remember fill cost!) IFetch Dcd Exec Mem WB IFetch Dcd Exec Mem WB IFetch Dcd Exec Mem WB IFetch Dcd Exec Mem WB IFetch Dcd Exec Mem WB IFetch Dcd Exec Mem WB Program Flow Time Pipelining Overhead How many instructions? How many cycles? Why are they not the same? Fill Costs Suppose we pipeline different numbers of instructions. What is the overhead of pipelining? Ideal pipelined machine- 1.0 ns/cycle, CPI=1, 10 instructions- 1.0 ns/cycle, CPI=1, 1000 instructions- 1.0 ns/cycle, CPI=1, 100,000 instructions Pentium 4 Pipeline 12: Trace cache next instruction pointer 34: Trace cache fetch 5: Drive- Up to 3 ops now sent into op queue 68: Allocate and rename- Each op enters 1 queue, up to 3 ops into queue 9: Queue (in-order queue within queue) Pentium 4 Pipeline 1012: Schedule- 812 entry mini-op queue, arbitrates for one of 4 issue ports 1314: Issue...
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This note was uploaded on 10/17/2011 for the course CPE 315 taught by Professor Staff during the Spring '11 term at Cal Poly.

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lectureweek5_1 - Computer Architecture CSC/CPE 315...

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