HW3-sol - Pi is specified by one level but Gi is specified...

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1 CSE 341: Computer Organization Spring 2011 Solution to HW #3 7) Gate delays for ripple-carry-adder and CLA adder. For ripple-carry-adder, the delay is 16 x 2 = 32 units. For the CLA adder, it is 5 gate delays. This is because C4 is represented in terms of Pi and Gi.
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Unformatted text preview: Pi is specified by one level but Gi is specified by two levels using pi and gi. So, the worst case for this next level of abstraction is two levels of logic. pi and gi can be implemented in one level logic. So, total delay is 2+2+1=5 units....
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This document was uploaded on 10/20/2011.

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